Fusion Family of Mixed Signal FPGAs
Revision 4
2-183
Table 2-109 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
Applicable to Standard I/Os
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.66
7.07
0.04
1.00
0.43
7.20
6.23
2.07
2.15
ns
–1
0.56
6.01
0.04
0.85
0.36
6.12
5.30
1.76
1.83
ns
–2 2
0.49
5.28
0.03
0.75
0.32
5.37
4.65
1.55
1.60
ns
4 mA
Std.
0.66
7.07
0.04
1.00
0.43
7.20
6.23
2.07
2.15
ns
–1
0.56
6.01
0.04
0.85
0.36
6.12
5.30
1.76
1.83
ns
–2
0.49
5.28
0.03
0.75
0.32
5.37
4.65
1.55
1.60
ns
6 mA
Std.
0.66
4.41
0.04
1.00
0.43
4.49
3.75
2.39
2.69
ns
–1
0.56
3.75
0.04
0.85
0.36
3.82
3.19
2.04
2.29
ns
–2
0.49
3.29
0.03
0.75
0.32
3.36
2.80
1.79
2.01
ns
8 mA
Std.
0.66
4.41
0.04
1.00
0.43
4.49
3.75
2.39
2.69
ns
–1
0.56
3.75
0.04
0.85
0.36
3.82
3.19
2.04
2.29
ns
–2
0.49
3.29
0.03
0.75
0.32
3.36
2.80
1.79
2.01
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on