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參數(shù)資料
| 型號： | M14C64 |
| 廠商： | 意法半導體 |
| 英文描述： | Memory Card IC 64/32 Kbit Serial IC Bus EEPROM |
| 中文描述： | 記憶卡IC 64/32千位串行IC總線的EEPROM |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 126K |
| 代理商： | M14C64 |
M14C64, M14C32
8/14
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 9.
This is followed by another START condition from
the master and the device select is repeated with
the RW
bit set to ‘1’. The memory acknowledges
this, and outputs the byte addressed. The master
must
not
acknowledge the byte output, and termi-
nates the transfer with a STOP condition.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. How-
ever, in this case the master
does
acknowledge
Current Address Read
The memory has an internal address counter.
Each time a byte is read, this counter is increment-
ed. For the Current Address Read mode, following
a START condition, the master sends a device se-
lect with the RW bit set to ‘1’. The memory ac-
knowledges this, and outputs the byte addressed
by the internal address counter. The counter is
then incremented. The master must
not
acknowl-
edge the byte output, and terminates the transfer
with a STOP condition, as shown in Figure 9.
Figure 9. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select bytes of a Random Read (in the 1
st
and 4
th
bytes) must be identical.
S
DEV SEL *
BYTE ADDR
BYTE ADDR
S
DEV SEL
DATA OUT 1
AI01105C
DATA OUT N
S
S
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
RANDOM
ADDRESS
READ
S
S
DEV SEL *
DATA OUT
SEQUENTIAL
CURRENT
READ
S
DATA OUT N
S
DEV SEL *
BYTE ADDR
BYTE ADDR
SEQUENTIAL
RANDOM
READ
S
DEV SEL *
DATA OUT 1
S
ACK
R/W
NO ACK
ACK
R/W
ACK
ACK
ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
ACK
ACK
ACK
R/W
ACK
ACK
R/W
ACK
NO ACK
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