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參數(shù)資料
| 型號(hào)： | M14C64 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Memory Card IC 64/32 Kbit Serial IC Bus EEPROM |
| 中文描述： | 記憶卡IC 64/32千位串行IC總線的EEPROM |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大?。?/td> | 126K |
| 代理商： | M14C64 |
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M14C64, M14C32
4/14
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
8 bits to the SDA bus line (with the most significant
bit first). These bits represent the Device Select
Code (7 bits) and a RW bit.
The seven most significant bits of the Device Se-
lect Code are the Device Type Identifier, according
to the I
2
C bus definition. For the memory device,
Figure 5. I
2
C Bus Protocol
SCL
SDA
SCL
SDA
SDA
START
CONDITION
SDA
INPUT
SDA
CHANGE
AI00792
STOP
CONDITION
1
2
3
7
8
9
MSB
ACK
START
CONDITION
SCL
1
2
3
7
8
9
MSB
ACK
STOP
CONDITION
Table 5. Device Select Code
1
Note: 1. The most significant bit, b7, is sent first.
Device Code
Chip Enable
RW
b7
b6
b5
b4
b3
b2
b1
b0
Device Select
1
0
1
0
0
0
0
RW
Note: 1.
b15 to b13 are Don’t Care on the M14C64 series.
b15 to b12 are Don’t Care on the M14C32 series.
Table 3. Most Significant Byte
b15
b14
b13
b12
b11
b10
b9
b8
Table 4. Least Significant Byte
b7
b6
b5
b4
b3
b2
b1
b0
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