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參數(shù)資料
| 型號： | M14C04DD |
| 廠商： | 意法半導體 |
| 英文描述： | M14C04 Die Description |
| 中文描述： | M14C04模具描述 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大小： | 108K |
| 代理商： | M14C04DD |
M14C16, M14C04
4/13
Write Operations
Following a START condition the master sends a
Device Select code with the RW
bit set to ’0’, as
shown in Table 4. The memory acknowledges it
and waits for a byte address, which provides ac-
cess to the memory area. After receipt of the ad-
dress, the memory again responds with an
acknowledge and waits for the data byte. Writing
in the memory may be inhibited if input pin WC is
taken high.
Any write command with WC=1 (during a period of
time from the START condition until the end of the
address) will not modify the memory content and
will NOT be acknowledged on data bytes, as
shown in Figure 5.
Figure 4. I
2
C Bus Protocol
SCL
SDA
SCL
SDA
SDA
START
CONDITION
SDA
INPUT
SDA
CHANGE
AI00792
STOP
CONDITION
1
2
3
7
8
9
MSB
ACK
START
CONDITION
SCL
1
2
3
7
8
9
MSB
ACK
STOP
CONDITION
Table 3. Device Select Code
1
Note: 1. A10, A9 and A8 correspond to the most significant bits of the memory array address word.
Device Code
Chip Enable
RW
b7
b6
b5
b4
b3
b2
b1
b0
M14C16 Select
1
0
1
0
A10
A9
A8
RW
M14C04 Select
1
0
1
0
0
0
A8
RW
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