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參數(shù)資料
| 型號(hào)： | M12S64322A-6BG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PBGA90 |
| 封裝： | 13 X 8 MM, LEAD FREE, BGA-90 |
| 文件頁數(shù)： | 27/46頁 |
| 文件大?。?/td> | 746K |
| 代理商： | M12S64322A-6BG |
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ES MT
M12S64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2007
Revision
:
1.0
27/46
Current
State
Precharging
CS
RAS
CAS
WE
BA
X
X
X
BA
BA
BA
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
X
ADDR
X
X
X
CA
RA
A10/AP
X
X
X
X
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
ACTION
Note
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
L
L
X
H
H
H
L
L
L
X
H
H
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
NOP
Idle after t
RP
NOP
Idle after t
RP
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after t
RDL
ILLEGAL
NOP
Row Active after t
RCD
NOP
Row Active after t
RCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after t
RC
NOP
Idle after t
RC
ILLEGAL
ILLEGAL
ILLEGAL
NOP
Idle after 2clocks
NOP
Idle after 2clocks
ILLEGAL
ILLEGAL
ILLEGAL
2
2
2
4
2
2
2
2
Row
Activating
Refreshing
Mode
Register
Accessing
Abbreviations :
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M12S64322A-6TG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7BG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7TG | 512K x 32 Bit x 4 Banks Synchronous DRAM |
| M13S128168A | 2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
| M13S128168A-5BG | 2M x 16 Bit x 4 Banks Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12S64322A-6TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
| M12S64322A-7TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Synchronous DRAM |
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