參數(shù)資料
型號: M12S128168A-10TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 15/44頁
文件大?。?/td> 967K
代理商: M12S128168A-10TG
ES MT
Write command
(CS ,CAS ,
WE
= Low, RAS = High)
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first
write data in burst can be input with this command with subsequent data on following
clocks.
Read command
(CS ,CAS = Low, RAS ,
WE
= High)
Read data is available afterCAS latency requirements have been met.
This command sets the burst start address given by the column address.
M12S128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.0
Publication Date
:
Nov. 2006
15/44
CBR (auto) refresh command
( CS , RAS , CAS = Low,
WE
,
CKE = High)
This command is a request to
begin the CBR refresh operation. The
refresh address is generated internally.
Before executing CBR refresh, all
banks must be precharged.
After this cycle, all banks will be in
the idle (precharged) state and ready
for a row activate command.
During t
RC
period (from refresh
command
to
refresh
command), the M12L128168A cannot
accept any other command.
or
activate
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相關代理商/技術參數(shù)
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M12S128168A-7TG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM
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