參數資料
型號: M12L2561616A-7BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 4M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54
封裝: 8 X 13 MM, LEAD FREE, BGA-54
文件頁數: 30/44頁
文件大?。?/td> 908K
代理商: M12L2561616A-7BG
ES MT
M12L2561616A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.2
Publication Date
:
Aug. 2007
30/44
Read & Write Cycle at Same Bank @ Burst Length = 4
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQM
A10/AP
BA0
BA1
CL =2
CL =3
Row Active
( A - Bank )
Read
( A - Bank )
Write
( A - Bank )
Row Active
( A - Bank )
Precharge
(A - Bank)
: D o n ' t C a r e
Qa1
Qa2
Qa3
Db1
Db2
Db3
D b0
Qa0
Ra
* N ot e2
Rb
Cb
R a
HI GH
t
R C D
t
R D L
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Rb
* N ot e3
Qa1
Qa2
Qa3
Db1
Db2
Db3
D b0
Qa0
t
R D L
* No te 3
Precharge
( A - Bank )
t
R C
* No te 1
Ca
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (t
SHZ
) after the clock.
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
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相關代理商/技術參數
參數描述
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M12L2561616A-7TG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Synchronous DRAM
M12L2561616A-7TG2K 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply
M12L2561616A-7TIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Synchronous DRAM