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參數(shù)資料
| 型號： | M1026-1Z-168.0400 |
| 英文描述： | VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| 中文描述： | 才能開發(fā)出復雜基于時鐘鎖相環(huán)AUTOSWITCH |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 322K |
| 代理商： | M1026-1Z-168.0400 |
M1025/26 Datasheet Rev 1.0
2
of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc.
●
Networking & Communications
●
www.icst.com
●
tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P r o d u c t D a t a S h e e t
P
IN
D
ESCRIPTIONS
Number
1,2,3,10,14,26
4
9
5
8
6
7
11,19,33
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
I/O
Ground
Configuration
Description
Power supply ground connections.
Input
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 9.
Output
Input
Power
Power supply connection, connect to +
3.3
V
Automatic/manual reselection mode for clock input:
Logic
1
automatic reselection upon clock failure
(non-revertive)
Logic
0
manual selection only (using
REF_SEL
)
Reference Acknowledgement pin for input mux state; outputs
the currently selected reference input pair:
Logic
1
indicates
nDIF_REF1, DIF_REF1
Logic
0
indicates
nDIF_REF0, DIF_REF0
12
AUTO
Input
Internal pull-down resistor
1
13
REF_ACK
Output
15
16
17
18
20
FOUT
nFOUT
P_SEL1
P_SEL0
nDIF_REF1
Output
No internal terminator
Clock output pair. Differential LVPECL (CML, LVDS available).
Internal pull-down resistor
1
Note 1: For typical values of internal pull-down and pull-UP resistors, see
DC Characteristics
on pg. 11.
Note 2: Biased toVcc/2, with 50k
to Vcc and 50k
to ground. See
Differential Inputs Biased to VCC/2
on pg. 11.
Note 3: See
LVCMOS Output
in
DC Characteristics
on pg. 11.
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5,
P Divider Look-Up Table (LUT),
on
pg. 4.
Input
Biased to Vcc/2
2
Internal pull-down resistor
1
Internal pull-down resistor
1
Referenc
e clock input selection.
LVCMOS/LVTTL:
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
Biased to Vcc/2
2
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
1
No internal connection.
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
21
DIF_REF1
22
REF_SEL
Input
23
nDIF_REF0
Input
24
25
27
28
29
30
DIF_REF0
NC
MR_SEL3
MR_SEL2
MR_SEL0
MR_SEL1
Input
Internal pull-down resistor
1
M and R divider value selection. LVCMOS/ LVTTL.
See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)
onpg. 3.
31
LOL
Output
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase.
3
Logic
1
indicates loss of lock.
Logic
0
indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1
- Narrow loop bandwidth
, R
IN
= 2100k
.
Logic
0
- Wde bandwidth
, R
IN
= 100k
.
32
NBW
Input
Internal pull-UP resistor
1
34,35,36
DNC
Do Not Connect.
Table 2: Pin Descriptions
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