參數(shù)資料
型號(hào)： M-ORT82G52BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁(yè)數(shù)： 72/94頁(yè)
文件大小： 2104K
代理商： M-ORT82G52BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
74
Package Information
Package Pinouts
Table 32 provides the package pin and pin function for the ORT82G5 FPSC and packages. The bond pad name is
identied in the PIO nomenclature used in the ispLEVER System software design editor. The Bank column pro-
vides information as to which output voltage level bank the given pin is in. The Group column provides information
as to the group of pins the given pin is in. This is used to show which VREF pin is used to provide the reference
voltage for single-ended limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a
given group, then the VREF pin is available as an I/O pin.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specic die, it is indicated as a note in the device column for
the FPGA. The tables provide no information on unused pads.
As shown in the pair columns in Table 32, differential pairs and physical locations are numbered within each bank
(e.g., L19C-A0 is the nineteenth pair in an associated bank). A ‘C’ indicates complementary differential, whereas a
‘T’ indicates true differential. An _A0 indicates the physical location of adjacent balls in either the horizontal or ver-
tical direction. Other physical indicators are as follows:
_A1 indicates one ball between pairs.
_A2 indicates two balls between pairs.
_D0 indicates balls are diagonally adjacent.
_D1 indicates balls are diagonally adjacent, separated by one physical ball.
VREF pins, shown in the Pin Description column in Table 32, are associated to the bank and group (e.g.,
VREF_TL_01 is the VREF for group one of the Top Left (TL) bank.t
Table 32. ORT82G5 680-Pin PBGAM Pinout
BM680 VDDIO Bank
VREF Group
I/O
Pin Description
Additional Function
BM680 Pair
AB20
—
Vss
—
C3
—
VDD33
—
E4
—
O
PRD_DATA
RD_DATA/TDO
—
F5
—
I
PRESET_N
RESET_N
—
G5
—
I
PRD_CFG_N
RD_CFG_N
—
D3
—
I
PPRGRM_N
PRGRM_N
—
A2
0 (TL)
—
VDDIO0
—
F4
0 (TL)
7
IO
PL2D
PLL_CK0C/HPPLL
L21C_A0
G4
0 (TL)
7
IO
PL2C
PLL_CK0T/HPPLL
L21T_A0
B3
0 (TL)
—
VDDIO0
—
C2
0 (TL)
7
IO
PL3D
—
L22C_D0
B1
0 (TL)
7
IO
PL3C
VREF_0_07
L22T_D0
A1
—
Vss
VSS
—
J5
0 (TL)
7
IO
PL4D
D5
L23C_A0
H5
0 (TL)
7
IO
PL4C
D6
L23T_A0
B7
0 (TL)
—
VDDIO0
—
E3
0 (TL)
8
IO
PL4B
—
L24C_A0
F3
0 (TL)
8
IO
PL4A
VREF_0_08
L24T_A0
C1
0 (TL)
8
IO
PL5D
HDC
L25C_D0
D2
0 (TL)
8
IO
PL5C
LDC_N
L25T_D0
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