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| 型號： | M-ORT82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 39/94頁 |
| 文件大?。?/td> | 2104K |
| 代理商： | M-ORT82G52BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
44
The data rate selection bits, TXHR and RXHR, in the channel conguration registers must be congured to carry
the same value and the PRBS Generator and Checker are excluded by setting the PRBS conguration bit to 0. The
8b/10b encoder/decoder is not in the loopback path. Table 13 summarizes the settings of the control interface reg-
ister conguration bits for high-speed serial loopback.
Table 13. High-Speed Serial Loopback Conguration Bit Denitions
Parallel Loopback at the SERDES Boundary
In this parallel loopback differential data are received at the HDINP_xx and HDINN_xx pins and are retransmitted
at the HDOUTP_xx and HDOUTN_xx pins. The loopback path is at the interface between the SERDES blocks and
the MUX and DEMUX blocks and uses the parallel 10-bit buses at these interfaces (see Figure 25 and Figure 26).
The loopback connection is made such that the input signals to the TX SERDES block is the same as the output
signals from the RX SERDES block. In this parallel loopback mode, the MRWDxx[39:0] signal lines remain active
and the TWDxx[31:0], TCOMMAxx[3:0] and TBIT9xx[3:0] signal lines are not used. This mode is normally used for
tests where serial test data is received from and transmitted to either test equipment or via a serial backplane to a
remote card and is the basic loopback path shown earlier in Figure 24(b).
The data rate selection bits TXHR and RXHR in the channel conguration registers must be congured to carry the
same value and the PRBS generator and checker are excluded by setting the PRBS conguration bit to 0. Also, the
8b/10b encoder and decoder are excluded from the loopback path by setting the 8b10bT and 8b10bR conguration
bits to 0. Table 14 illustrates the control interface register conguration for the parallel loopback.
Register
Address
Bit Value
Bit Name
Comments
30002, 30012, 30022,
30032, 30102, 30112,
30122, 30132
Bit 0 = 0 or 1
TXHR
Set to 0 or 1. TXHR and RXHR bits must be set to the same
value.
30002, 30012, 30022,
30032, 30102, 30112,
30122, 30132
Bit 7 = 0 or 1
8B10BT
Set to 0 or 1. If set to 0, the 8b/10b encoder is excluded from
the loopback path. The 8b/10b encoder and decoder selec-
tion control bits must both be set to the same value.
30003, 30013, 30023,
30033, 30103, 30113,
30123, 30133
Bit 0 = 0 or 1
RXHR
Set to 0 or 1. TXHR and RXHR bits must be set to the same
value.
30003, 30013, 30023,
30033, 30103, 30113,
30123, 30133
Bit 3 = 0 or 1
8B10BR
Set to 0 or 1. If set to 0, the 8b/10b decoder is excluded from
the loopback path. The 8b/10b encoder and decoder selec-
tion control bits must both be set to the same value.
30004, 30014, 30024,
30034, 30104, 30114,
30124, 30134
Bit 0 = 0
PRBS
Set to 0.
30801, 30901
Bit 0 =1 (Channel A)
Bit 1 = 1 (Channel B)
Bit 2 = 1 (Channel C)
Bit 3 = 1 (Channel D)
LOOPENB_xx Set any of the bits 0-3 to 1 to do serial loopback on the corre-
sponding channel.* The high speed serial outputs will not be
active.
*This test mode can also be set using TESTEN_xx in place of LOOPENB_xx. In that case, Test Mode must be set to 00000.
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