參數(shù)資料
型號(hào)： M-ORT82G52BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁(yè)數(shù)： 50/94頁(yè)
文件大小： 2104K
代理商： M-ORT82G52BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
54
Control Registers (Read/Write), xx=[AA, ...,BD]
30800 - Ax
30900 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
ENBYSYNC_xx
00
ENBYSYNC_xx = 1 Enables Receiver Byte Synchronization for Channel
xx.
ENBYSYNC_xx = 0 on device reset.
[4]xA
[5]xB
[6]xC
[7]xD
LCKREFN_xx
LCKREFN_xx = 0 Locks the receiver PLL to ref reference clock for
Channel xx.
LCKREFN_xx =1 = Locks the receiver to data for Channel xx.
NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also
zero.
LCKREFN_xx = 0 on device reset.
30801 - Ax
30901 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
LOOPENB_xx
Enable Loopback Mode for Channel xx. When LOOPEN_xx=1, the
transmitter high-speed output is looped back to the receiver high-speed
input. This mode is similar to high-speed loopback mode enabled by
TESTMODE_xx except that LOOPEN_xx disables the high-speed serial
output.
LOOPEN_xx=0 on device reset.
[4]xA
[5]xB
[6]xC
[7]xD
NOWDALIGN_xx
Word Align Disable Bit. When NOWDALIGN_xx=1, receiver word align-
ment is disabled for Channel xx.
NOWDALIGN_xx=0 on device reset.
30802
30902
[0:7]
Reserved for future use
30803
30903
[0:7]
Reserved for future use
30810 - Ax
30910 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
DOWDALIGN_xx
00
Word Realign Bit. When DOWDALIGN_xx transitions from 0 to 1, the
receiver realigns on the next comma character for Channel xx.
NOWDALIGN_xx=0 on device reset.
[4]xA
[5]xB
[6]xC
[7]xD
FMPU_STR_EN
_xx
Enable multi-channel alignment for Channel xx. When
FMPU_STR_EN_xx=1, the corresponding channel participates in multi-
channel alignment.
FMPU_STR_EN_xx=0 on device reset.
30811 - Ax
30911 - Bx
[0:1]
xA
[2:3]
xB
[4:5]
xC
[6:7]
xD
FMPU_SYNMOD
E_xx[0:1]
00
Sync mode for xx
00 = No channel alignment
10 = Twin channel alignment
01 = Quad channel alignment
11 = 8 channel alignment
30812
30912
[0:7]
Reserved for future use
30813
30912
[0:7]
Reserved for future use
30823
30923
[0:7]
Reserved for future use
30830
30930
[0:7]
Reserved for future use
Table 20. Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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