參數(shù)資料
型號： LXT9880AGE
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 86/96頁
文件大?。?/td> 1309K
代理商： LXT9880AGE
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
86
Datasheet
5.3.5
Interrupt Status/Mask Registers
The interrupt status and mask registers are described in
Table 65 and Table 66
. Refer to
Table 64
for bit assignments.
Table 63. Port Status Registers
Name
Type
1
Addr
Description
Port Link Status
R
098
A read of this register will reflect the current link status of the 4 twisted-pair ports
within a LXT980 chip. A
‘
1
’
indicates that the port is currently in the LINK_GOOD
state. (default = 0s)
Port Polarity Status
R
099
A read of this register will reflect the current polarity status of the 4 twisted-pair
ports within a LXT980 chip. A
‘
1
’
indicates that the polarity has been crossed for a
given port. (default = 0s)
Port Partition Status
R
09A
A read of this register will reflect the current partition status of all 5 ports within a
LXT980 chip. A
‘
1
’
indicates that the port has been partitioned out of the repeater.
A
‘
0
’
is read if the port is connected. (default = 0s)
Port Speed Status
R
09C
Indicates the current status of each port.
0 = port is connected at 10 Mbps
1 = port is connected at 100 Mbps
Port Isolation Status
(Fast Ethernet Only)
R
09D
Indicates the current isolation status of each port operating in Fast Ethernet.
Fast Ethernet Port Isolation (Clause 27.3.2 of 802.3u)
1. R = Read Only
Table 64. Interrupt Status/Mask Register Bit Assignments
31:8
7
6
5
4
3
2
1
0
Reserved
Far-End
Fault
Reserved
Jabber
Isolate
Partition
FCC
Source
Address
Change
Speed
Change
Detected
Table 65. Interrupt Status/Mask Register
Name
Type
Addr
Description
Interrupt Status Register
R(/W)
1
0AE
This register captures status bits within the LXT980 and holds them.
Refer to
Table 66
for bit descriptions.
Interrupt Mask Register
R/W
0AF
This register allows masking of individual interrupts.
0 = do not mask (default)
1 = mask
1. R(/W) When the register clear bit (bit11) in the repeater configuration register is set to a
‘
0
’
, this register is cleared upon
reading.
If the register clear bit is set to a
‘
1
’
, these register bit(s) are cleared by writing a
‘
1
’
to the appropriate bit(s).
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