LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
84
Datasheet
5.3.2
General Port Control Registers
The General Port Control Register set is described in
Table 59
. Refer to
Table 58
for the General
Port Control Registers bit assignments.
Table 58. General Port Control and Status Register Bit Assignments
31:5
4
3
2
1
0
Rsvd
Port 5 (MII)
Port 4
Port 3
Port 2
Port 1
Table 59. General Port Control Registers
Name
Type
Addr
Description
Port Alternate Partition
Algorithm Control
R/W
094
LXT980
Provides per-port selection of partition algorithms.
0 = normal (default)
1 = alternate
Speed
Normal
Alternate
10M
Un-partition a port when data
can be
either received or
transmitted
from the port for
450-560 bit times without a
collision on that port.
Un-partition a port
only when
data can be transmitted
to the
port for 450-560 bit times
without a collision on that port.
100M
Un-partition a port
only when
data can be transmitted
to the
port for 450-560 bit times
without a collision on that port.
Un-partition a port when data
can be
either received or
transmitted
from the port for
450-560 bit times without a
collision on that port.
LXT980A
Provides per-port selection of partition algorithms.
0 = normal
1 = alternate (default)
Speed
Normal
Alternate
10M
Un-partition a port when data can be
either received or
transmitted
from the port for 450-560 bit times without a collision
on that port.
100M
Un-partition a port
only when
data can be transmitted
to the
port for 450-560 bit times
without a collision on that port.
Un-partition a port when data
can be
either received or
transmitted
from the port for
450-560 bit times without a
collision on that port.
Port Enable
R/W
095
This register controls whether a port is enabled/disabled. If the MGR_PRES
signal is Low on power up, then all ports will be disabled until such time that
management software re-enables them. Otherwise the ports will power on
enabled.
0 = disable, 1 = enable (default = 1).