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參數(shù)資料
| 型號： | LXT9860HC |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 41/96頁 |
| 文件大?。?/td> | 1309K |
| 代理商： | LXT9860HC |
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Datasheet
41
2.6.1
Serial Clock
SERCLK is a bidirectional pin; direction control is provided by the RECONFIG input. If
RECONFIG is High, the LXT980 will drive SERCLK at 625 kHz. If RECONFIG is Low,
SERCLK is an input, between 0 and 2 MHz. There is no lower bound to how slow the interface can
operate. The clock can be stopped after each operation, as long as an idle (16 ones in a row) is
transmitted first.
2.6.2
Serial Data I/O
The serial data pins, SRX and STX, should be tied together. The SRX input is compared with the
STX output. If a mismatch occurs, STX goes to a high impedance. STX is driven on the falling
edge of SERCLK. SRX is sampled on the rising edge. Refer to Test Specifications (
Figure 40 on
page 77
) for timing information.
2.6.3
Read and Write Operations
Normally the network manager directs read and write operations to a specific LXT980 device
using a two-part address consisting of HubID and ChipID. The interface allows up to 127 32-bit
registers to be read at one time. Up to two registers can be written at a time.
Some registers may be automatically cleared when subsequent write operations are performed on
other registers. Refer to the
“
Auto-Clearing Registers
”
section, which follows.
2.6.3.1
Management Frame Format
The SMI uses a simple frame format, which is shown in
Figure 11 on page 43
.
Table 19
describes
the individual fields.
Table 20 on page 43
shows how the bits for the header field would be stored
in memory, assuming that they are transmitted LSB to MSB, low address to high address.
Table 21
on page 43
lists the command set and
Table 22 on page 44
provides a variety of typical packets.
All frames begin and end with a flag of consisting of
“
01111110
”
. All fields are transmitted LSB
first. Zero-bit stuffing is required if more than five 1s in a row appear in the header, data or CRC
fields. In addition, all operations directed to the device must be followed by an idle (ten 1s in a
row), and the first operation must be preceded with an idle.
Figure 10. Typical Serial Bus Architecture
LXT918
LXT918
RMON &
Repeater MIB
Support
LXT980
8530 Serial
Controller
Network
Management
User
Definable
Partitioning
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