參數(shù)資料
型號: LXT9785BC
英文描述: LAN TRANSCEIVER|OCTAL|BGA|241PIN|PLASTIC
中文描述: 網(wǎng)絡(luò)收發(fā)器|八路|的BGA | 241PIN |塑料
文件頁數(shù): 36/68頁
文件大?。?/td> 1177K
代理商: LXT9785BC
LXT9784
Low-Power Octal PHY
36
Datasheet
100BASE-TX SMII Data Transmission
The data is signaled in ten-bit segments, where each segment represents a new byte of data. Each
segment is delimited by a SYNC pulse (every 10 clocks).
When TX_EN in the serial bit stream is de-asserted, then TXD[7:0] are the inter-frame control bits
(for a direct MAC to MAC connection). When the TX_EN bit asserts, the PHY accepts the data
stream on the TXD
n
line.
Figure 10
shows the format of the SMII transmit serial stream.
2.4
10BASE-T Mode
2.4.1
10BASE-T Receiver
2.4.1.1
10BASE-T Manchester Decoder
The LXT9784 PHYs perform Manchester decoding and timing recovery when in 10BASE-T
mode. The Manchester-encoded data stream is decoded from TPIP
n
and TPIN
n
to separate
Receive Clock and Receive Data signals from the differential signal. This data is assembled to
nibbles and transferred to the RMII/SMII.
10BASE-T RMII Data Reception
RMII data is transferred in di-bits at a 50 MHz rate. Therefore the data on RXD
n_
<1:0> is changed
every 10 clock cycles.
Figure 9. RMII Data Transmission
TXEN
n
TXD
n
_0
MCLK
TXD
n
_1
Preamble
0
0
0
0
0
0
0
0
1
x
x
x
x
x
0
∫∫
0
1
1
1
1
1
1
1
1
x
x
x
x
x
0
∫∫
SFD
Data
∫∫
∫∫
∫∫
∫∫
Figure 10. SMII Transmit Data Serial Stream
SYNC
MCLK
Transmit stream direction
TXD
n
TX_ER
TX_EN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
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