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參數(shù)資料
| 型號(hào)： | LXT9782 |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 38/68頁 |
| 文件大?。?/td> | 1177K |
| 代理商： | LXT9782 |
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LXT9784
—
Low-Power Octal PHY
38
Datasheet
2.4.1.6
10BASE-T Full Duplex
The LXT9784 PHYs support 10 Mbps full duplex by disabling the collision and the carrier sense
functions. This allows each LXT9784 PHY to transmit and receive simultaneously, achieving up to
20 Mbps of network bandwidth. The configuration is done through auto-negotiation.
2.4.2
10BASE-T Transmit
2.4.2.1
10BASE-T Manchester Encoder
When TXEN
n
is asserted, the PHY accepts di-bit data on the RMII TXD
n_
[1:0] lines, or serial
stream data on the SMII TXD
n
line. After the clocked data is serialized into a 10 Mbps serial
stream, the 20 MHz clock performs the Manchester encoding. The Manchester code always has a
mid-bit transition. If the data to be transmitted is "1", then the transition is from low to high. If the
value is "0" then the transition is from high to low. The boundary transition (such as between cell
times) occurs only when the data changes from bit to bit: if "10" then the change is from high to
low; if "01" then the change is from low to high.
10BASE-T RMII Data Transmission
The data is transferred in di-bits at a 50 MHz rate. Therefore the data on TXD
n_
[1:0] is valid for 10
clock cycles for each di-bits.
10BASE-T SMII Data Transmission
The data is signaled in ten-bit segments. Each segment is delimited by a SYNC pulse (every 10
clocks). In 10M mode, the data rate is one-tenth the 100M rate, therefore each segment is repeated
ten times so that every 10 segments represent a new byte of data.
2.4.2.2
10BASE-T Driver and Filter
Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented
inside the chip. This allows the two technologies to share the same magnetics. The LXT9784
supports both technologies through one pair of TPOP
n
and TPON
n
pins and by externally sharing
the same magnetics.
In 10 Mbps mode, the LXT9784 PHYs begin transmitting the serial Manchester bit stream within 3
bit times (300 ns) after the assertion TXEN
n
. In 10-Mbps mode the line drivers use a pre-distortion
algorithm to improve jitter tolerance. The line drivers reduce their drive level during the second
half of
“
wide
”
(100 ns) Manchester pulses and maintain a full drive level during all narrow (50 ns)
pulses and the first half of the wide pulses. The LXT9784
’
s advanced wave-shaping circuitry
prevents overcharging during wide pulses, a major source of jitter.
2.5
MDI/MDI-X Function
When connecting Ethernet devices together, there are two types of cables in use: straight-through
and crossed-over cables. In a typical connection, DTE to Switch, cross-over is implemented in the
Switch MAU. In this case a straight-through cable is required. However, in case that a connection
is required between two MAUs of the same type, then an external cross-over cable is required. In
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相關(guān)代理商/技術(shù)參數(shù) |
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| LXT9782BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|OCTAL|BGA|272PIN|PLASTIC |
| LXT9782HC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|OCTAL|QFP|208PIN|PLASTIC |
| LXT9784 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Transceiver Hardware Integrity Function Overview |
| LXT9784BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|OCTAL|BGA|324PIN|PLASTIC |
| LXT9784BE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|OCTAL|BGA|324PIN|PLASTIC |
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