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參數(shù)資料
| 型號： | LXT9761 |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 30/68頁 |
| 文件大?。?/td> | 1177K |
| 代理商： | LXT9761 |
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LXT9784
—
Low-Power Octal PHY
30
Datasheet
The PHYs can individually auto-negotiate with their link partners, and thereby auto-configure their
speeds of operation. The MDI/MDIX auto-switching configuration is done prior to Auto-
Negotiation.
The RMII or SMII mode is selected by mode select balls MODE<2:0>.
Three balls select the general operation of the device.
Table 11
shows the balls settings for the
different modes of operation.
2.3
100BASE-TX Mode
2.3.1
100BASE-TX Receiver
Each receive subsection of the LXT9784 PHYs accepts 100BASE-TX MLT-3 data on TPIP
n
and
TPIN
n
(where
“
n
”
is the port number). Due to the advanced digital signal processing design
techniques employed, the PHYs accurately receive valid data from CAT5 UTP and type 1 STP
cable over distances well in excess of 100 meters.
2.3.1.1
Digital Adaptive Equalizer
The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer filter
coefficients are digitally adapted based on the shape of the received signal, equalizing the signal to
exceed IEEE specification bit error rate (BER) performance for transmission over 100 meters of
CAT 5 twisted pair.
2.3.1.2
Receive Clock and Data Recovery
The clock recovery circuit uses advanced DSP technology to compensate for signal distortion and
jitter. The circuitry recovers the 125 MHz clock and data from the equalizer output and presents the
data to the NRZI-to-NRZ converter.
Table 11. LXT9784 Modes of Operation
Mode Pins
MII
Mode
MCLK
Frequency
2
1
1
0
0
0
0
Reserved
0
0
1
RMll
50 MHz
0
1
0
SMII
125 MHz
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Manufacturing
Test Mode
1. MODE 2 pin must be set to zero for normal operation.
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