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參數(shù)資料
| 型號(hào)： | LXT9761 |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 29/68頁 |
| 文件大?。?/td> | 1177K |
| 代理商： | LXT9761 |
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Low-Power Octal PHY
—
LXT9784
Datasheet
29
2.0
Functional Description
2.1
Introduction
The LXT9784 is a single chip transceiver device containing eight independent 10/100 Ethernet
transceivers with RMII and/or SMII Interfaces. The LXT9784 supports per-port speed auto-
configuration. Each of the eight PHYs represents a highly-integrated, physical-layer interface
solution designed for 10Mbps and/or 100 Mbps Ethernet systems based on the IEEE 802.3
Standard 10BASE-T and 100BASE-TX specifications.
100BASE-TX is an IEEE 802.3 Standard physical layer specification for use over two pairs of
Category 5 unshielded twisted-pair (UTP CAT 5) or Type 1 shielded twisted pair (STP Type 1)
cable. 100BASE-TX defines a signaling scheme not only for 100 Mbps, but also provides CSMA/
CD compatibility with the 10Mbps IEEE 802.3 Standard 10BASE-T signaling standard.
Each PHY of the LXT9784 complies with the IEEE 802.3u Auto-Negotiation section, and with the
IEEE 802.3x Full- Duplex Flow Control section. The interface to each PHY complies with the
current RMII and SMII specifications.
The LXT9784 PHYs incorporate all active circuitry required to interface 10/100 Mbps Ethernet
controllers and CSMA/CD MAC components to 100BASE-TX and 10BASE-T networks. Each
PHY supports a direct glue less interface to all standard RMII or SMII components.
Figure 4
shows
how the LXT9784 PHY fits into a typical 10/100 Mbps Ethernet switch design.
2.2
LXT9784 Configuration
The LXT9784 has a common Management Data Interface (MDI) for the eight PHYs. This is a
serial interface and complies with the IEEE 802.3Standard MII for MDC and MDIO signals. In all
modes of operation the PHYs can be configured individually using the MII management interface.
Figure 4. LXT9784 PHY in a 10/100 Mbps Ethernet Solution
Controller or
MAC
RMII / SMII
System Bus Interface
RMII
or
SMII
Magnetics
Tx D
Rx D
LXT9784
1 of 8
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