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參數(shù)資料
| 型號(hào)： | LXT970AQC |
| 英文描述： | LAN TRANSCEIVER|SINGLE|CMOS|QFP|64PIN|PLASTIC |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器|單|的CMOS | QFP封裝| 64管腳|塑料 |
| 文件頁(yè)數(shù)： | 65/68頁(yè) |
| 文件大小： | 1177K |
| 代理商： | LXT970AQC |
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Low-Power Octal PHY
—
LXT9784
Datasheet
65
17.9
Carrier Sense
Disable
Controls the RX100 CRS disable function
1 = CRS disable.
default 0 = CRS enable.
RW
17.8
Reserved
Must be set to zero during write
RW
17.7
Auto-Negotiation
Loopback
1 = Auto-Negotiation Loopback.
default 0 = Auto-Negotiation normal mode.
RW
17.6
MDI Tri-state
1 = MDI Tri-state (transmit driver tri-states)
default 0 = Normal operation
RW
17.5
Force Polarity
1 = Reversed polarity
default 0 = Normal polarity operation.
RW
17.4
Auto Polarity Disable
1 = Auto Polarity disabled.
default 0 = Auto Polarity enabled.
RW
17.3
SQE Disable
1 = 10BASE-T squelch test disabled.
default 0 = Normal squelch operation
RW
17.2
Extended Squelch
Extended Squelch control.
1 = 10BASE-T extended squelch control enabled.
0 = 10BASE-T extended squelch control disabled.
RW
17.1
Link Integrity Disable
1 = Link disabled.
default 0 = Normal Link Integrity operation.
RW
P
17.0
Jabber Function
Disable
1 = Jabber disabled.
default 0 = Normal Jabber operation.
RW
Table 52. Register 18 (12 Hex) PHY Interrupt Register
Bit(s)
Name
Description
Type
1
18.15:2
Reserved
Constant
“
0
”
.
RO
18.1
Interrupt Enable
Enables the assertion of a specific PHY Interrupt line. However, bit 0 is not masked,
and the interrupt bit will remain visible.
1 = enable the assertion of the interrupt line.
default 0 = disable the interrupt line.
RW
18.0
Link Status
Interrupt
Reflects the PHY link integrity changing. The bit is self-cleared after any read cycle.
1 = a change on PHY link status was detected.
RO
SC
1. Refer to
Table 42 on page 60
for Type definitions.
Table 53. Reg 19 (13 Hex) 100 BASE-TX RCV False Carrier Counter
Bit(s)
Name
Description
Type
1
19[15:0]
False Carrier
Sense
A 16 bit counter that increments for each false carrier event (bad SSD). The counter
stops when full (and does not roll over.) Self clears on read.
RO
SC
1. Refer to
Table 42 on page 60
for Type definitions.
Table 51. Register 17 (11 Hex) Special Control (Continued)
Bit(s)
Name
Description
Type
1
1. Refer to
Table 42 on page 60
for Type definitions.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT970AQC.B11 | 制造商:Intel 功能描述: |
| LXT970ATC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecomm/Datacomm |
| LXT970QC | 制造商:LEVEL ONE 功能描述: 制造商:Level One 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP 制造商:Level One Communications 功能描述:LAN Transceiver, Single, 64 Pin, Plastic, QFP |
| LXT971A | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet PHY Transceiver |
| LXT971ABC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:LAN TRANSCEIVER|SINGLE|CMOS|BGA|64PIN|PLASTIC |
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