參數(shù)資料
型號: LXT970AQC
英文描述: LAN TRANSCEIVER|SINGLE|CMOS|QFP|64PIN|PLASTIC
中文描述: 網(wǎng)絡收發(fā)器|單|的CMOS | QFP封裝| 64管腳|塑料
文件頁數(shù): 26/68頁
文件大?。?/td> 1177K
代理商: LXT970AQC
LXT9784
Low-Power Octal PHY
26
Datasheet
Table 8. RMII Mode Signal Descriptions
Ball ID
Signal Name
Type
1
Signal Description
V1
CRSDV0
O
Carrier Sense / Receive Data Valid, Ports 0-7.
CRS
and RXDV signals of the MII interface are collapsed
into one signal. This signal indicates to the LXT9784
that traffic is present on the link, and that the incoming
data on the RXD<1:0> pins is valid.
U3
CRSDV1
P1
CRSDV2
N3
CRSDV3
H2
CRSDV4
F1
CRSDV5
D2
CRSDV6
B1
CRSDV7
L18
RXER0
O
Receive Error, Ports 0-7.
The RXER signal indicates
to the LXT9784 that an error has occurred during
frame reception.
M20
RXER1
M19
RXER2
M18
RXER3
N20
RXER4
N19
RXER5
N18
RXER6
P20
RXER7
V2, V3
RXD0_1, RXD0_0
O
Receive Data, Ports 0-7.
In 100 Mbps and 10 Mbps
mode, data is transferred across these two lines.
U2, U1
RXD1_1, RXD1_0
P2, P3
RXD2_1, RXD2_0
N2, N1
RXD3_1, RXD3_0
H3, G1
RXD4_1, RXD4_0
G3, G2
RXD5_1, RXD5_0
D3, C1
RXD6_1, RXD6_0
C3, C2
RXD7_1, RXD7_0
W1, W2
TXD0_1, TXD0_0
I
Transmit Data, Ports 0-7.
In 100 Mbps and 10 Mbps
mode, data is transferred across these two lines
T3, T2
TXD1_1, TXD1_0
R1, R2
TXD2_1, TXD2_0
M3, M2
TXD3_1, TXD3_0
J2, J3
TXD4_1, TXD4_0
E1, F3
TXD5_1, TXD5_0
E2, E3
TXD6_1, TXD6_0
A2, B3
TXD7_1, TXD7_0
1. Refer to
Table 1 on page 11
for Signal Type Definitions.
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