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參數(shù)資料
| 型號： | LXT917QC |
| 英文描述： | LAN Transceiver |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器 |
| 文件頁數(shù)： | 9/42頁 |
| 文件大?。?/td> | 561K |
| 代理商： | LXT917QC |
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Flexible Quad Ethernet Repeater
—
LXT914
Datasheet
9
Table 1. LXT914 Power, Ground and Clock Signal Descriptions
Pin #
Symbol
I/O
Description
PLCC
PQFP
1
2
3
26
49
55
67
68
—
—
27
61
62
69
70
88
89
90
91
93
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
—
—
—
—
—
—
—
—
—
—
Power Supply Inputs.
These pins each require a +5 VDC power supply.
The various pins may be supplied from a single power source, but special
de-coupling requirements may apply. Each VCC input must be within ±0.3
V of every other VCC input.
9
34
36
38
39
46
52
58
—
39
41
43
44
58
65
66
73
99
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
—
—
—
—
—
—
—
—
—
Ground.
These pins provide ground return paths for the various power
supply pins.
37
42
RBIAS
—
Bias.
This pin provides bias current for the internal circuitry. The 100 μA
bias current is provided through an external 12.4 k
resistor to ground.
10
4
BCLKIO
I/O
Backplane Clock.
This 10 MHz clock synchronizes multiple repeaters on a
common backplane. In the synchronous mode, BCLKIO must be supplied
to all repeaters from a common external source. In the asynchronous
mode, BCLKIO is supplied only when a repeater is outputting data to the
bus. Each repeater outputs its internally recovered clock when it takes
control of the bus. Other repeaters on the backplane then sync to BCLKIO
for the duration of the transmission.
11
6
SYSCLK
I
System Clock.
The required 20 MHz system clock is input at this pin.
Clock must have a 40-60 duty cycle with < 10 ns rise time.
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