參數(shù)資料
型號(hào)： LXT363LE
英文描述： PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
中文描述： 的PCM收發(fā)器|單|的T 1（DS1的）|的CMOS | QFP封裝| 44PIN |塑料
文件頁(yè)數(shù)： 21/52頁(yè)
文件大?。?/td> 1187K
代理商： LXT363LE
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
—
LXT361
Datasheet
21
3.5.2.2
Quasi-Random Signal Source (QRSS)
See
Figure 10
. For T1 operation, the Quasi-Random Signal Source (QRSS) is a 2
20
-1 pseudo-
random bit sequence (PRBS) with no more than 14 consecutive zeros. For E1 operation, QRSS is
2
15
-1 PRBS with inverted output. Setting bits CR2.EPAT0 = 0 and CR2.EPAT1 = 1 enables this
function.
The QRSS pattern is normally locked to TCLK; but if there is no TCLK, MCLK is the clock
source. Bellcore Pub 62411 defines the T1 QRSS transmit format and ITU G.703 defines the E1
format.
With QRSS transmission enabled, it is possible to insert a logic error into the transmit data stream
by causing a Low-to-High transition on INSLER. However, if no logic or bit errors are to be
inserted into the QRSS pattern, INSLER must remain Low. Logic Error insertion waits until the
next bit if the current bit is
“
jammed
”
. When there are more than 14 consecutive 0s, the output is
jammed to a 1.
Furthermore, a bipolar violation in the QRSS pattern is possible by causing a Low-to-High
transition on the INSBPV pin, regardless of whether the device is in Bipolar or Unipolar mode.
Choosing QRSS mode also enables the QRSS Pattern Detection in the receive path. The QRSS
pattern is synchronized when there are fewer than four errors in 128 bits. The PSR.QRSS bit
provides an indication of QRSS pattern synchronization. This bit goes Low when no QRSS pattern
detected (
i
.
e
., when there are more than four errors in 128 bits). The TQRSS bit in the Transition
Status Register indicates that QRSS status has changed since the last QRSS Interrupt Clear
command.
The LXT361 can generate an interrupt to indicate that QRSS detection has occurred, or that
synchronization is lost. The interrupt is enabled when ICR.CQRSS = 0.
3.5.2.3
In-Band Network Loop Up or Down Code Generator
The LXT361 can transmit in-band Network Loop Up or Loop Down code. The Loop Up code is
00001; Loop Down code is 001. A Loop Up code transmission occurs when Control Register #2
bits EPAT0 = 1 and EPAT1 = 0. A Loop Down code transmission requires that both EPAT0 and
EPAT1 = 1.
With this mode enabled, logic errors and bipolar violations can be inserted into the transmit data
stream. Inserting a logic error requires a Low-to-High transition in INSLER (pin 3). If no logic or
bit errors are to be inserted, INSLER must remain Low. Inserting a bipolar violation requires a
Low-to-High transition on the INSBPV pin, regardless of unipolar or bipolar operation.
Figure 10. QRSS Mode
* If Enabled
INT*
相關(guān)PDF資料
PDF描述
LXT363PE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|LDCC|28PIN|PLASTIC
LXT363QE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
LXT360LE PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|QFP|44PIN|PLASTIC
LXT360PE PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|LDCC|28PIN|PLASTIC
LXT384BE Telecomm/Datacomm
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT363PE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|LDCC|28PIN|PLASTIC
LXT363QE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
LXT36X/35X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LXT36x/35x - LXT36x/35x Master Clock Requirements
LXT380/4 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LXT380/4 - LXT380/4 Octal T1/E1 LIUs Interfacing with the Transwitch Octal Framers
LXT380/LXT381 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LXT380/LXT381 - LXT380/1 Frequently Asked Questions
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*