參數(shù)資料
型號： LXT361PE
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁數(shù)： 16/52頁
文件大?。?/td> 1187K
代理商： LXT361PE
LXT361
—
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
16
Datasheet
3.4
Jitter Attenuation
A Jitter Attenuation Loop (JAL) with an Elastic Store (ES) provides jitter attenuation as shown in
the Test Specifications section. The JAL requires no special circuitry, such as an external quartz
crystal or high-frequency clock (higher than the line rate). Its timing reference is MCLK.
Bit CR1.JASEL0 enables or disables the JA circuit. With bit CR1.JASEL0 = 1, bit CR1.JASEL1
controls the JA circuit placement (see
Table 7 on page 27
). The ES can be either a 32 x 2-bit or 64
x 2-bit register depending on the value of bit CR3.ES64 (see
Table 10 on page 28
.)
The device clocks data into the ES using either TCLK or RCLK depending on whether the JA
circuitry is in the transmit or receive data path, respectively. Data is shifted out of the elastic store
using the dejittered clock from the JAL. When the FIFO is within two bits of overflowing or
underflowing, the ES adjusts the output clock by
1
/
8
of a bit period. The ES produces an average
delay of 16 bits (or 32 bits, with the 64-bit ES option selected) in the associated data path. When
the Jitter Attenuator is in the receive path, the output RCLK transitions smoothly to MCLK in the
event of a LOS condition.
The Transition Status Register bits TSR.ESOVR and TSR.ESUNF indicate an elastic store
overflow or underflow, respectively. Note that these are sticky bits that once set to 1, remain set
until the host reads the register. The ES can also provide a maskable interrupt on either overflow or
underflow.
3.5
Diagnostic Mode Operation
The LXT361 offers multiple diagnostic modes as listed in
Table 4
. The diagnostic modes are
selected by setting the appropriate register bits as described in the following paragraphs.
3.5.1
Loopback Modes
3.5.1.1
Local Loopback
See
Figure 4
and
Figure 5
. Local loopback is selected by setting CR2.ELLOOP to 1. LLOOP
inhibits the receiver circuits. The transmit clock and data inputs (TCLK and TPOS/TNEG or
TDATA) loop back through the jitter attenuator (if enabled) and show up at RCLK and RPOS/
RNEG or RDATA. Note that during LLOOP, the JASEL input is strictly an Enable/Disable control;
it does not affect the placement of the JAL. If JA is enabled, it is active in the loopback circuit. If
JA is bypassed, it is not active in the loopback circuit.
The transmitter circuits are unaffected by LLOOP. LXT361 transmits the TPOS/TNEG or TDATA
inputs (or a stream of 1s if TAOS is asserted) normally. When used in this mode, the transceiver
can function as a stand-alone jitter attenuator.
Table 4. Diagnostic Mode Summary
Diagnostic Mode
Interrupt
Maskable
Loopback Modes
Local Loopback (LLOOP)
No
Analog Loopback (ALOOP)
No
相關(guān)PDF資料
PDF描述
LXT362LE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
LXT362PE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|LDCC|28PIN|PLASTIC
LXT362QE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
LXT363LE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
LXT363PE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|LDCC|28PIN|PLASTIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT361QE 制造商:LEVEL ONE 功能描述: 制造商:LEVEL ONE 功能描述:DATACOM, PCM TRANSCEIVER, PQFP44
LXT362 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
LXT362LE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
LXT362PE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|LDCC|28PIN|PLASTIC
LXT362QE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*