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參數資料
| 型號： | LXT331QH |
| 英文描述： | LINE INTERFACE|CMOS|QFP|44PIN|PLASTIC |
| 中文描述： | 線路接口|的CMOS | QFP封裝| 44PIN |塑料 |
| 文件頁數： | 26/32頁 |
| 文件大?。?/td> | 395K |
| 代理商： | LXT331QH |
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LXT331
—
Dual T1/E1 Line Interface Unit
26
Datasheet
High level input voltage
4,5
VIH
2.0
-
-
V
Low level input voltage
4,5
VIL
-
-
0.8
V
High level output voltage
4,5
VOH
2.4
-
-
V
IOUT = - 400
μΑ
Low level output voltage
4,5
VoL
-
-
0.4
V
IOUT = 1.6 mA
Input leakage current
6
ILLD
0
-
± 10
μ
A
Input leakage current
7
ILLM
0
-
± 50
μ
A
Three-state leakage current
4
ISL
-
-
± 10
μ
A
TTIP/TRING leakage current
ITR
-
-
1.2
mA
In power down and tri-state
Table 11. Analog Specifications
(Over Recommended Operating Range)
Parameter
Min
Typ
1
Max
Unit
Test Conditions
AMI output pulse amplitudes
DSX-1
2.4
3.0
3.6
V
measured at the DSX
E1 (120
)
2.7
3.0
3.3
V
measured at line side
E1 (75
)
2.13
2.37
2.61
V
measured at line side
Transmit amplitude variation with supply
3
-
1
2.5
%
Recommended output load at TTIP and TRING
-
75
-
Driver output impedance
3
-
3
10
@ 772 kHz
Jitter added by the transmitter
2
10 Hz - 8kHz
3
-
0.005
0.01
UI
T1 Jitter Bands
8 kHz - 40 kHz
3
-
0.015
0.025
UI
10 Hz - 40 Hz
3
-
0.02
0.025
UI
Broad band
-
0.03
0.05
UI
Jitter added by the transmitter
2
20 Hz - 100 kHz
-
-
0.05
UI
E1 Jitter Band
Output power levels
3
DSI 2 kHz BW
@ 772 kHz
12.6
-
17.9
dBm
@ 1544 kHz
-29
-
-
dB
Positive-to-negative pulse imbalance
-
-
0.5
dB
Differential input impedance
-
40
-
k
Sensitivity below DSX (0 dB = 2.4 V)
(max 6 dB cable attenuation)
13.6
-
-
dB
500
-
-
mV
1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
2. Input signal at TCLK is jitter-free.
3. Not production tested, but guaranteed by design and other correlation methods.
Table 10. Electrical Characteristics
(Over Recommended Operating Range)
Parameter
Sym
Min
Typ
1
Max
Unit
Test Conditions
1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
2. 100% 1s density and maximum line length. Driving a line load over operating temperature range. Includes device and load.
Digital input levels are within 10% of the supply rails. Digital outputs are driving a 50 pF capacitive load.
3. 100% 1s density and maximum line length. Driving a line load (corresponding to Rt value of 9.1
and 1:2 transformer ratio)
over operating range. include device and load. Digital input levels are within 10% of the supply rails. Digital outputs are driving
a 50 pF capacitive load.
4. Functionality of pins depends on mode.
5. Output drivers will output CMOS logic levels into CMOS loads.
6. All digital input pins.
7. For MTIP0, MRING0, MTIP1 AND MRING1.
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