參數(shù)資料
型號(hào)： LXT331QH
英文描述： LINE INTERFACE|CMOS|QFP|44PIN|PLASTIC
中文描述： 線路接口|的CMOS | QFP封裝| 44PIN |塑料
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 395K
代理商： LXT331QH
Dual T1/E1 Line Interface Unit
—
LXT331
Datasheet
13
2.3.1
Host Mode Control
Host mode is selected when a clock is applied to the SPE pin. Each of the two LIUs contains a pair
of data registers, one for command inputs and one for status outputs. An SIO transaction is initiated
by a falling pulse on one of the two Port Select pins, PS0 or PS1. Only one LIU can be selected at a
time. A High-to-Low transition on PS
n
is required for each subsequent access to the Host mode
registers. If both PS0 and PS1 are active simultaneously, Port 0 has priority over Port1.
The LIU addressed by the PS
n
pulse responds by writing the incoming serial word (at the SDI pin)
into its command register.
Figure 5 on page 15
shows an SIO write operation. The 16-bit serial
word consists of an 8-bit Command/Address byte and an 8-bit Data byte. If the command word
contains a read request, the addressed LIU subsequently outputs the contents of its status register
onto the SDO pin.
Figure 6 on page 16
shows an SIO read operation. The Clock Edge (CLKE) signal determines
when the SDO output is valid (relative to SCLK) as follows:
If CLKE = High, SDO is valid on the rising edge of SCLK. If CLKE = Low, SDO is valid on the
falling edge of SCLK. Refer to Test Specifications for SIO timing.
2.3.1.1
Serial Input Word
Figure 5 on page 15
shows the Serial Input data structure. The LXT331 is addressed by setting bit
A4 in the Address/Command byte, corresponding to address 16. Bit 1 of the serial Address/
Command byte provides Read/Write (R/W) control when the chip is accessed. The R/W bit is set to
logic 1 to read the data output byte from the chip, and set to logic 0 to write the input data byte to
the chip.
The second 8 bits of a write operation (the Data Input byte) clear the Driver Performance Monitor
(DPM) and Driver Fail Monitor (DFM) interrupts, reset the chip, and control diagnostic modes.
The first and second bits (D0-1) clear and/or mask the DPM and DFM interrupts, and the last 3 bits
(D5-7) control operating modes (normal and diagnostic) and chip reset. Refer to
Table 3
for details
on bits D5-7.
Figure 4. LXT331 Driver Performance Monitor
Pulse Width
Monitor
Pulse Width
Monitor
Pulse Width
Monitor
Pulse Width
Monitor
+
+
+
+
-
-
-
-
MTIP
+2.5 V
+790 mV
MRING
+2.5 V
-790 mV
C1
C2
C3
C4
A1
A2
O1
CLK
CNTR63
zero*
DPM
I
C
R
R
O
S
Q
A
B
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