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參數(shù)資料
| 型號(hào)： | LXT331PH |
| 英文描述： | LINE INTERFACE|CMOS|LDCC|44PIN|PLASTIC |
| 中文描述： | 線路接口|的CMOS | LDCC | 44PIN |塑料 |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 395K |
| 代理商： | LXT331PH |
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Dual T1/E1 Line Interface Unit
—
LXT331
Datasheet
7
Table 1. Pin Descriptions
Pin
PLCC
Pin
QFP
Symbol
I/O
1
Description
1
39
TRSTE
DI
Tristate Enable
. Forces all output pins to tri-state when held High and forces chip into
reset mode. Holds reset mode for 6
μ
s after TRSTE returns Low.
2
40
TCLK0
DI
Transmit Clock — Port 0
. 1.544 MHz for T1, 2.048 MHz for E1. The transmit data
inputs are sampled on the falling edge of TCLK. If TCLK is pulled Low, the transmit
drivers are powered down and TTIP and TRING transmit outputs go to a high
impedance state.
3
4
41
42
TPOS0
TNEG0
DI
DI
Transmit Positive and Negative Data, Port 0
. These pins drive the positive and
negative sides of the bipolar input pair for port 0. Data to be transmitted onto the line
is input at these pins.
5
6
43
44
NMRK0
PMRK0
DO
DO
Receive
Negative
and
Positive
Marks, Port 0
. These pins are the data outputs from
port 0. A signal on NMRK corresponds to receipt of a negative pulse on RTIP/RRING.
A signal on PMRK corresponds to receipt of a positive pulse on RTIP/RRING. NMRK/
PMRK outputs are Return-to-Zero (RZ).
7
1
CLKE
DI
Clock Edge Select
(Host mode)
. When CLKE is High, SDO is valid on the rising
edge of SCLK.When CLKE is Low, SDO is valid on the falling edge of SCLK.
ALOOP0
DI
Analog Local Loopback Enable, Port 0
(Hardware mode)
. When ALOOP is High,
the RTIP/RRING inputs from the port 0 twisted-pair line are disconnected and the
transmit data outputs (TTIP/TRING) are routed back into the receiver. For normal
operation, hold ALOOP Low.
8
2
SCLK
DI
Serial Clock
(Host mode)
. Shifts data into or out of the serial interface register of the
selected port.
TAOS0
DI
Transmit All Ones Enable, Port 0
(Hardware mode)
. When TAOS is High, the
TPOS/TNEG input is ignored and the selected port transmits a stream of ones at the
TCLK frequency. With no TCLK, the MCLK input becomes the transmit reference. For
normal operation, hold TAOS Low. Refer to
page 18
.
9
3
PS0
DI
Port Select, Port 0
(Host mode)
.
Selects the serial interface registers of Port 0. For
each read or write operation, PS0 must transition from High to Low, and remain Low.
LEN20
DI
Line Length Equalizer 2, Port 0
(Hardware mode)
. Determines the shape and
amplitude of the transmit pulse. Refer to
Table 2 on page 12
10
4
INT0
DO
Interrupt, Port 0
(Host mode)
. Goes Low to flag the host processor that Port 0 has
changed state. INT0 is an open drain output and must be tied to VCC through a
resistor.
LEN10
DI
Line Length Equalizer 1, Port 0
(Hardware mode)
.
Determines the shape and
amplitude of the transmit pulse. Refer to
Table 2 on page 12
11
5
GND
DI
Unused (
Host mode)
.
Must be tied to Ground.
LEN00
DI
Line Length Equalizer 0, Port 0
(Hardware mode)
.
Determines the shape and
amplitude of the transmit pulse. Refer to
Table 2 on page 12
12
6
MCLK
DI
Master Clock.
1.544 MHz for T1, 2.048 MHz for E1. Can be held Low if TCLK is
present.
13
7
GND
S
Ground.
Ground return for VCC power supply.
14
8
TTIP0
AO
Transmit Tip, Port 0
. The TTIP and TRING pins are differential driver outputs
designed to drive a 35-200
load. Line matching resistors and transformers can be
selected to give the desired pulse height.
15
9
TGND0
S
Ground, Port 0 Transmit Driver.
Ground return for TVCC0 power supply.
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; S = Power
Supply
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