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參數(shù)資料
| 型號： | LXT331PH |
| 英文描述： | LINE INTERFACE|CMOS|LDCC|44PIN|PLASTIC |
| 中文描述： | 線路接口|的CMOS | LDCC | 44PIN |塑料 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大小： | 395K |
| 代理商： | LXT331PH |
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Dual T1/E1 Line Interface Unit
—
LXT331
Datasheet
19
2.5
Initialization & Reset
Upon initial power up, the transceiver is held static until the power supply reaches approximately 3
V. Upon crossing this threshold, the device clears all internal registers. TCLK is the transmit
reference, and MCLK is the bias reference. The PLLs are continuously calibrated.
The transceiver can be reset from the Host or Hardware mode. In Host mode, reset is commanded
by writing 1s to TST and ALOOP, and a 0 to TAOS (bits D5, D6 and D7, respectively, of the SIO
input data byte). In either mode, reset is commanded by holding the TRSTE pin High for
approximately 200 ns. All output signals are tri-stated at this time. In Hardware mode, the falling
edge of TRSTE initiates reset for the entire chip. Host mode resets the selected port SIO registers
to 0. Reset is not generally required for the port to be operational.
Figure 9. TAOS with Analog Loopback
Figure 10. Analog Loopback
Timing &
Control
TTIP
TRING
RTIP
RRING
Transmit All Ones =ALOOP
with ALOOP
TAOS
TCLK
TPOS
TNEG
1
TAOS
1
PMRK
NMRK
Timing &
Control
TTIP
TRING
RTIP
RRING
Analog Loopback
ALOOP
1
TAOS
0
PMRK
NMRK
TCLK
TPOS
TNEG
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