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參數(shù)資料
| 型號： | LU82541ER |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 82541ER Gigabit Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 1000M bps, LOCAL AREA NETWORK CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-196 |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 284K |
| 代理商： | LU82541ER |
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82541ER Gigabit Ethernet Controller
Datasheet
9
3.2.2
Arbitration Signals (2)
3.2.3
Interrupt Signal (1)
3.2.4
System Signals (3)
IDSEL#
I
Initialization Device Select.
The Initialization Device Select signal is used by the
82541ER as a chip select signal during configuration read and write transactions.
DEVSEL#
STS
Device Select.
When the Device Select signal is actively driven by the 82541ER, it
signals notifies the bus master that it has decoded its address as the target of the
current access. As an input, DEVSEL# indicates whether any device on the bus has
been selected.
VIO
P
VIO.
The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI
signaling environment). It is used as the clamping voltage.
Note:
VIO should be connected to 3.3V Aux or 5V Aux in order to be compatible with
the pull-up clamps specification.
Symbol
Type
Name and Function
REQ#
TS
Request Bus.
The Request Bus signal is used to request control of the bus from the
arbiter. This signal is point-to-point.
GNT#
I
Grant Bus.
The Grant Bus signal notifies the 82541ER that bus access has been
granted. This is a point-to-point signal.
Symbol
Type
Name and Function
INTA#
TS
Interrupt A.
Interrupt A is used to request an interrupt of the 82541ER. It is an active
low, level-triggered interrupt signal.
Symbol
Type
Name and Function
CLK
I
PCI Clock.
The PCI Clock signal provides timing for all transactions on the PCI bus and
is an input to the 82541ER device. All other PCI signals, except the Interrupt A (INTA#)
and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All other timing
parameters are defined with respect to this edge.
M66EN
I
66 MHz Enable.
M66EN indicates whether the system bus is enabled for 66MHz
RST#
I
PCI Reset.
When the PCI Reset signal is asserted, all PCI output signals are floated
and all input signals are ignored.
Most of the internal state of the 82541ER is reset on the de-assertion (rising edge) of
RST#.
Symbol
Type
Name and Function
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LU82541ER 862931 | 制造商:Intel 功能描述:TABOR; GIGABIT ETHERNET CONTROLLER, SINGLE PORT, PB-FREE 2LI - Trays |
| LU82541ER S L7QU | 制造商:Intel 功能描述:GIGABIT ETHERNET CONTROLLER 制造商:Intel 功能描述:TABOR; GIGABIT ETHERNET CONTROLLER, SINGLE PORT, PB-FREE 2LI - Tape and Reel |
| LU82541ER 862931 | 制造商:Intel 功能描述:Ethernet ICs Controller IEEE 10/ 100/1000 Mbps BGA196 |
| LU82541ER S L7QU | 制造商:Intel 功能描述:Ethernet ICs Controller IEEE 10/ 100/1000 Mbps BGA196 |
| LU82541GI | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82541 Family of Gigabit Ethernet Controllers |
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