參數(shù)資料
型號(hào): LTNT
廠商: Linear Technology Corporation
英文描述: 24-Bit No Latency ADC with Differential Input and Reference in MSOP
中文描述: 24位不具有差動(dòng)輸入和ADC的參考延遲,采用MSOP
文件頁(yè)數(shù): 15/40頁(yè)
文件大?。?/td> 503K
代理商: LTNT
LTC2411/LTC2411-1
15
Table 3. LTC2411/LTC2411-1 State Duration
State
Operating Mode
CONVERT
Internal Oscillator
Duration
133ms, Output Data Rate
7.5 Readings/s
F
O
= LOW (LTC2411)
(60Hz Rejection)
F
O
= HIGH (LTC2411)
(50Hz Rejection)
F
O
= LOW (LTC2411-1)
(Simultaneous 50Hz/60Hz Rejection)
F
O
= External Oscillator
with Frequency f
EOSC
kHz
(f
EOSC
/2560 Rejection)
160ms, Output Data Rate
6.2 Readings/s
147ms, Output Data Rate
6.8 Readings/s
External Oscillator
20510/f
EOSC
s, Output Data Rate
f
EOSC
/20510 Readings/s
SLEEP
DATA OUTPUT
As Long As CS = HIGH Until CS = LOW and SCK
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 1.83ms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 256/f
EOSC
ms
(32 SCK cycles)
As Long As CS = LOW But Not Longer Than 32/f
SCK
ms
(32 SCK cycles)
Internal Serial Clock
F
O
= LOW/HIGH (LTC2411)
(Internal Oscillator)
F
O
= LOW (LTC2411-1)
(Internal Oscillator)
F
O
= External Oscillator with
Frequency f
EOSC
kHz
External Serial Clock with
Frequency f
SCK
kHz
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 9) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2411/LTC2411-1 create their own se-
rial clock by dividing the internal conversion clock by 8. In
the External SCK mode of operation, the SCK pin is used
as input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CS pin. If SCK is HIGH or float-
ing at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 8), provides the result
of the last conversion as a serial bit stream (MSB first)
during the data output state. In addition, the SDO pin is
used as an end of conversion indicator during the conver-
sion and sleep states.
When CS (Pin 7) is HIGH, the SDO driver is switched to a
high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 7), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2411/LTC2411-1 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with
CS=LOW).
APPLICATIOU
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