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參數(shù)資料
| 型號(hào)： | LTNT |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 24-Bit No Latency ADC with Differential Input and Reference in MSOP |
| 中文描述： | 24位不具有差動(dòng)輸入和ADC的參考延遲，采用MSOP |
| 文件頁數(shù)： | 10/40頁 |
| 文件大?。?/td> | 503K |
| 代理商： | LTNT |
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LTC2411/LTC2411-1
10
Figure 1
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 8):
Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = V
CC
), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
SCK (Pin 9):
Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as the digital input for the external serial
interface clock during the Data Output period. A weak
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode is
determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
F
O
(Pin 10):
Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. For the LTC2411, when the F
O
pin is connected to V
CC
(F
O
= V
CC
), the converter uses its internal oscillator and the
digital filter first null is located at 50Hz. When the F
O
pin is
connected to GND (F
O
= OV), the converter uses its internal
oscillator and the digital filter first null is located at 60Hz.
For the LTC2411-1, the converter provides simultaneous
50Hz/60Hz rejection with the F
O
pin connected to GND.
When F
O
is driven by an external clock signal with a
frequency f
EOSC
, the converters use this signal as their
system clock and the digital filter first null is located at a
frequency f
EOSC
/2560.
W
FU
PIU
AUTOCALIBRATION
AND CONTROL
DAC
DECIMATING FIR
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
ADC
∑
∫
∫
∫
GND
V
CC
IN
+
IN
–
SDO
SCK
REF
+
REF
–
CS
F
O
(INT/EXT)
2411 FD
–
+
+
–
TEST CIRCUITS
1.69k
SDO
2411 TA03
Hi-Z TO V
OH
V
OL
TO V
V
OH
TO Hi-Z
C
LOAD
= 20pF
1.69k
SDO
2411 TA04
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
C
LOAD
= 20pF
V
CC
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