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| 型號(hào)： | LTNN |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 24-Bit No Latency ADC with Differential Input and Reference in MSOP |
| 中文描述： | 24位不具有差動(dòng)輸入和ADC的參考延遲，采用MSOP |
| 文件頁(yè)數(shù)： | 13/40頁(yè) |
| 文件大?。?/td> | 503K |
| 代理商： | LTNN |
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LTC2411/LTC2411-1
13
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2411/LTC2411-1 Status Bits
Bit 31
EOC
0
0
0
0
Bit 30 Bit 29 Bit 28
DMY
SIG
0
1
0
1
0
0
0
0
Input Range
V
IN
≥
0.5 V
REF
0V
≤
V
IN
< 0.5 V
REF
–0.5 V
REF
≤
V
IN
< 0V
V
IN
< –0.5 V
REF
MSB
1
0
1
0
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
Table 2. LTC2411/LTC2411-1 Output Data Format
Differential Input Voltage
V
IN
*
V
IN
*
≥
0.5 V
REF
**
0.5 V
REF
** – 1LSB
0.25 V
REF
**
0.25 V
REF
** – 1LSB
0
–1LSB
–0.25 V
REF
**
–0.25 V
REF
** – 1LSB
–0.5 V
REF
**
V
IN
* < –0.5 V
REF
**
*The differential input voltage V
IN
= IN
+
– IN
–
.
**The differential reference voltage V
REF
= REF
+
– REF
–
.
Bit 31
EOC
0
0
0
0
0
0
0
0
0
0
Bit 30
DMY
0
0
0
0
0
0
0
0
0
0
Bit 29
SIG
1
1
1
1
1
0
0
0
0
0
Bit 28
MSB
1
0
0
0
0
1
1
1
1
0
Bit 27
Bit 26
Bit 25
…
Bit 0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
…
…
…
…
…
0
1
0
1
0
1
0
1
0
1
Figure 3. Output Data Timing
MSB
SIG
“0”
1
2
3
4
5
26
27
32
BIT 0
BIT 27
BIT 5
LSB
24
BIT 28
BIT 29
BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2411 F03
Hi-Z
APPLICATIOU
W
U
U
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