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參數(shù)資料
| 型號： | LTC6946IUFD-1#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTEGER-N PLL W/VCO 28-QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標準包裝： | 73 |
| 類型： | 時鐘/頻率合成器（RF/IF），分數(shù)-N，整數(shù)-N， |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.74GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應商設(shè)備封裝： | 28-QFN（4x5） |
| 包裝： | 管件 |
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LTC6946
15
6946fa
OPERATION
CHARGE PUMP FUNCTIONS
The charge pump contains additional features to aid
in system start-up and monitoring. See Table 6 for a
summary.
Table 6. Charge Pump Function Bit Descriptions
BIT
DESCRIPTION
CPCHI
Enable High Voltage Output Clamp
CPCLO
Enable Low Voltage Output Clamp
CPDN
Force Sink Current
CPINV
Invert PFD Phase
CPMID
Enable Mid-Voltage Bias
CPRST
Reset PFD
CPUP
Force Source Current
CPWIDE
Extend Current Pulse Width
THI
High Voltage Clamp Flag
TLO
Low Voltage Clamp Flag
The CPCHI and CPCLO bits found in register h0A enable
the high and low voltage clamps, respectively. When CPCHI
is enabled and the CP pin voltage exceeds approximately
VCP+ – 0.9V, the THI status flag is set, and the charge pump
sourcing current is disabled. Alternately, when CPCLO is
enabled and the CP pin voltage is less than approximately
0.9V, the TLO status flag is set, and the charge pump sinking
current is disabled. See Figure 5 for a simplified schematic.
The CPMID bit also found in register h0A enables a resis-
tive VCP+/2 output bias which may be used to pre-bias
troublesome loop filters into a valid voltage range. When
using CPMID, it is recommended to also assert the CPRST
bit, forcing a PFD reset. Both CPMID and CPRST must be
set to “0” for normal operation.
The CPUP and CPDN bits force a constant ICP source or
sink current, respectively, on the CP pin. The CPRST bit
may also be used in conjunction with the CPUP and CPDN
bits, allowing a pre-charge of the loop to a known state,
if required. CPUP, CPDN, and CPRST must be set to “0”
to allow the loop to lock.
The CPWIDE bit extends the charge pump output current
pulse width by increasing the PFD reset path’s delay value
(see Figure 3). CPWIDE is normally set to 0.
Table 7. BD[3:0] Programming
BD[3:0]
B DIVIDE VALUE
fPFD (MHz)
0
8
<2.4
1
12
2.4 to 3.6
2
16
3.6 to 4.8
3
24
4.8 to 7.2
4
32
7.2 to 9.6
5
48
9.6 to 14
6
64
14 to 19
7
96
19 to 29
8
128
29 to 38
9
192
38 to 58
10
256
58 to 77
11
384
>77
12 to 15
Invalid
VCO
The integrated VCO is available in one of three frequency
ranges. The output frequency range may be further ex-
tended by utilizing the output divider (see Available Options
table, for more details). The wide frequency range of the
VCO, coupled with the output divider capability, allows the
LTC6946 to cover an extremely wide range of continuously
selectable frequencies.
VCO Calibration
The VCO must be calibrated each time its frequency is
changed by either fREF, the R divider, or N divider, but not
the O divider (see the Applications Information section for
the relationship between R, N, O, and the fREF, fPFD, fVCO
and fRF frequencies). The output frequency is then stable
over the LTC6946’s entire temperature range, regardless
of the temperature at which it was calibrated, until the
part is reset due to a power cycle or software power-on
reset (POR).
The output of the B divider is used to clock digital calibra-
tion circuitry as shown in the Block Diagram. The B value,
programmed with bits BD[3:0], is determined according
to Equation 1.
B ≥
fPFD
0.3MHz
(1)
The relationship between bits BD[3:0], the B value, and
fPFD is shown in Table 7.
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| LTC6946-x | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 20Msps Low Noise Dual ADC |
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