參數(shù)資料
型號： LTC6603CUF#TRPBF
廠商： Linear Technology
文件頁數(shù)： 16/24頁
文件大小： 0K
描述： IC FILTER LOWPASS 24-QFN
標(biāo)準(zhǔn)包裝： 2,500
濾波器類型： 低通
頻率 - 截止或中心： 80MHz
濾波器數(shù)： 2
濾波器階數(shù)： 9th
電源電壓： 2.7 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 24-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN 裸露焊盤（4x4）
包裝： 帶卷 (TR)
LTC6603
23
6603fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
TYPICAL APPLICATIONS
UF Package
24-Lead Plastic QFN (4mm
× 4mm)
(Reference LTC DWG # 05-08-1697)
LTC6603 Parallel Clock Control
LTC6603 SPI Clock Control
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
24
23
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ± 0.10
(4-SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 0105
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.45 ± 0.05
(4 SIDES)
3.10 ± 0.05
4.50 ± 0.05
PACKAGE
OUTLINE
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
6603 TA02
+INA
V+IN
V+A
V+D
–INA
+INB
–INB
CAP
GAIN1
GAIN0(D0)
GND
RBIAS
VOCM
+OUTA
–OUTA
+OUTB
–OUTB
CLKCNTL
SDO
SDI
LPF0(SCLK)
LPF1(CS)
CLKIO
SER
LTC6603
0.1
3V
12
16
3V
0.1μF
24
23
20
22
21
25
14
7
8
4
3
19
18
5
11
10
6
9
13
12
15
17
R3
R1
VOCM
R2
DIODES INC
DMN2004DWK
CLK1
CLK0
0
RBIAS1
fCLK1
0
1
RBIAS2
fCLK2
1
0
RBIAS3
fCLK3
1
RBIAS4
fCLK4
RBIAS1 > RBIAS2 OR RBIAS3
RBIAS =
RBIAS IN k
fCLK in MHz
R1 = RBIAS1 R2 =
R3 =
RBIAS4 =
CLK0
LPF1
LPF0
GAIN1
GAIN0
2472
fCLK
DESIGN PROCEDURE
1. CHOOSE fCLK1, fCLK2 AND fCLK3
2. CALCULATE RBIAS1, RBIAS2 AND RBIAS3
3. CALCULATE R2, R3 AND RBIAS4
RBIAS1 RBIAS2
RBIAS1 – RBIAS2
RBIAS1 RBIAS3
RBIAS1 – RBIAS3
R1 R2 R3
R1 (R2 + R3) + R2 R3
6603 TA03
+INA
V+IN
V+A
V+D
–INA
+INB
–INB
CAP
GAIN1
GAIN0(D0)
GND
RBIAS
VOCM
+OUTA
–OUTA
+OUTB
–OUTB
CLKCNTL
SDO
SDI
LPF0(SCLK)
LPF1(CS)
CLKIO
SER
LTC6603
0.1μF
3V
12
16
3V
0.1μF
24
23
20
22
21
25
14
7
8
4
3
19
18
5
11
10
6
9
13
12
15
17
CS
SCLK
SDI
VOUT
GND
V+
0.1μF
3V
4
5
6
3
2
1
R1
VB
VC R2
CS1
CS2
SCK
SDI
LTC2630
8-BIT DAC
IF R1 = 51.1k and R2 = 78.7k THEN
THE fCLK RANGE IS 12.36MHz to 80MHz
DAC VOUT RANGE 0V TO 2.5V
(USING THE LTC2630 INTERNAL REFERENCE)
R1 =
VC RANGE 0V to 2.5V, VB = 1.17V
IF VC = 0V THEN fCLK= fCLKHI
IF VC = 2.5V THEN fCLK= fCLKLO
5.282 1012
1.137fCLKHI + fCLKLO
, R2 =
5.282 1012
fCLKHI – fCLKLO
fCLK = 2.472 10
12
R1
+R2
R1 R2
VC
VB R2
PACKAGE DESCRIPTION
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