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參數(shù)資料
| 型號： | LTC6603CUF#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FILTER LOWPASS 24-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 濾波器類型： | 低通 |
| 頻率 - 截止或中心： | 80MHz |
| 濾波器數(shù)： | 2 |
| 濾波器階數(shù)： | 9th |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 帶卷 (TR) |
LTC6603
19
6603fa
APPLICATIONS INFORMATION
not independent as they are both set by the VOCM pin.
Figure 10 illustrates the distortion versus output common
mode voltage for a 2VP-P differential input voltage and a
common mode input voltage that is equal to mid-supply.
Figure 10. Distortion vs Common Mode Output Voltage
Connecting resistors between each input and V+IN will
pull the input common mode voltage up, increasing the
input signal swing. The resistance, RPULL-UP, necessary to
set the input common mode voltage, VICM, to any desired
level can be calculated by
RPULL UP =RCM
VSUPPLY
VICM
1
where
RCM = 40k80MHz/fCLK for LPF1=0, LPF0=0
RCM = 20k80MHz/fCLK for LPF1=0, LPF0=1
RCM = 5k80MHz/fCLK for LPF1=1
For example, if the lowpass cutoff frequency is set to
2.5MHz, 5k resistors connected between each input and
V+IN will set the input common mode voltage to mid-
supply.
Circuit A of Figure 12 is for a xed CLK and LPF0, LPF1
setting. If the clock varies or the LPF0, LPF1 setting changes
then Circuit B of Figure 12 should be used.
Due to the sampled data nature of the lter, an anti-aliasing
lter at the inputs is recommended.
The output common mode voltage is equal to the voltage
of the VOCM pin. The VOCM pin is biased to one-half of
the supply voltage by an internal resistive divider (see
Block Diagram). To alter the common mode output volt-
age, VOCM can be driven with an external voltage source
or resistor network. If external resistors are used, it is
important to note that the internal 2k resistors can vary
±30% (their ratio varies only ±1%). The lter outputs can
also be AC-coupled.
The LTC6603 can be interfaced to an A/D converter by pull-
ing CLKCNTL (Pin 5) to V+D.ThisconguresCLKIO(Pin15)
as a clock output, which can be used to drive the clock
input of the A/D converter. This allows the A/D converter
to be synchronized with the lter sampling clock, avoiding
“beat frequencies” and simplifying the board layout. Any
routing attached to the CLKIO pin should be as short as
possible, in order to minimize reections.
Similarly, the LTC6603 can be interfaced to another LTC6603
in a master/slave conguration as shown in Figure 13. This
COMMON MODE OUTPUT VOLTAGE (V)
0.8
DISTOR
TION
(dBc)
–60
–70
–65
–75
–80
1.0
1.4
6603 F10
1.8
1.6
1.2
RBIAS = 30.9k, VS = 3V,
GAIN = 24dB, TA = 25°C
SIGNAL FREQUENCY = 200kHz
HD3, LPF1 = 0, LPF0 = 1
HD3, LPF1 = 1
HD2, LPF1 = 0,
LPF0 = 1
HD2, LPF1 = 1
Interfacing to the LTC6603
TheinputandoutputcommonmodevoltagesoftheLTC6603
are independent. The input common mode voltage is set
by the signal source if DC-coupled, as shown in Figure 11.
If the inputs are AC-coupled, as shown in Figure 12
(Circuit A), the input common mode voltage will be pulled to
ground by an equivalent resistance of RCM,showninTable5.
This does not affect the lter’s performance as long as
the input amplitude is less than 0.5VP-P. At low lter gain
settings, a larger input voltage swing may be desired.
Figure 11. DC-Coupled Inputs
V+IN
V+A
V+D
+INA
–INA
VOCM
GND
LTC6603
0.1μF
DC-COUPLED INPUT
VIN (COMMON MODE) = (VIN+ + VIN–)/2
VOUT (COMMON MODE) = (VOUT+ + VOUT–)/2 = VSUPPLY/2
6603 F11
+OUTA
–OUTA
VSUPPLY
+
–
+
–
1μF
VOUT+
VOUT–
VIN+
VIN–
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| LTC6603IUF#TRPBF | 功能描述:IC FILTER LOWPASS 24-QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 濾波器 - 有源 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 濾波器類型:連續(xù)時間，帶通低通 頻率 - 截止或中心:150kHz 濾波器數(shù):4 濾波器階數(shù):8th 電源電壓:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) |
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