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參數(shù)資料
| 型號： | LTC4313CDD-2#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 2WIRE BUS BUFFER 8DFN |
| 標準包裝： | 121 |
| 類型： | 2線總線緩沖器 |
| Tx/Rx類型： | I²C Logic |
| 電容 - 輸入： | 10pF |
| 電源電壓： | 2.9 V ~ 5.5 V |
| 電流 - 電源： | 8.1mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-DFN（3x3） |
| 包裝： | 管件 |
LTC4313-1/LTC4313-2/
LTC4313-3
9
4313123f
of the LTC4313-1 and LTC4313-2 must be greater than
or equal to 0.9VCC. An example is shown in Figure 3
where the input bus voltage is greater than VCC. During a
rising edge, the input bus rise rate will be accelerated by
the RTA up to a voltage of 2.97V after which the bus rise
rate will reduce to a value that is determined by the bus
current and bus capacitance. The RTA turn-off voltage is
less than the bus supply and the bus is not overdriven.
Pull-Up Resistor Value Selection
To guarantee that the RTAs are activated during a rising
edge, the bus must rise on its own with a positive slew rate
of at least 0.4V/s. To achieve this, choose a maximum
RBUS using the formula:
RBUS ≤
VDD,BUS(MIN) VRTA(TH)
(
)
0.4
V
s
CBUS
(1)
RBUS is the pull-up resistor, VDD,BUS(MIN) is the minimum
bus pull-up supply voltage, VRTA(TH)isthevoltageatwhich
the RTA turns on and CBUS is the equivalent bus capaci-
tance. RBUS must also be large enough to guarantee that:
RBUS ≥
VDD,BUS(MAX) 0.4V
(
)
4mA
(2)
This criterion ensures that the maximum bus current is
less than 4mA.
applicaTions inForMaTion
Input to Output Offset Voltage
While propagating a logic low voltage on its SDA and SCL
pins, the LTC4313 introduces a positive offset voltage
between the input and output. When a logic low voltage
≥200mV is driven on any of the LTC4313’s clock or data
pins, the LTC4313 regulates the voltage on the opposite
side to a slightly higher value. This is illustrated in Equa-
tion 3, which uses SDA as an example:
VSDAOUT = VSDAIN + 50mV + 15
VDD,BUS
RBUS
(3)
In Equation 3, VDD,BUS is the output bus supply voltage
and RBUS is the SDAOUT bus pull-up resistance.
For driven logic low voltages < 200mV Equation 3 does
not apply as the saturation voltage of the open collector
outputtransistorresultsinahigheroffset.Foradriveninput
logic low voltage below 220mV, the output is guaranteed
to be below a VOL of 400mV for bus pull-up currents up to
4mA. See the Typical Performance Characteristics section
for offset variation as a function of the driven logic low
voltage and bus pull-up current.
Figure 3. Level Shift Application Where the SDAIN and SCLIN Bus Pull-Up
Supply Voltage Is Higher Than the Supply Voltage of the LTC4313
LTC4313-1
GND
VCC
4313123 F03
READY
SCLOUT
SDAOUT
ENABLE
SCLIN
SDAIN
SCL1
SDA1
R2
10k
C1
0.01F
R1
10k
5V
READY
SCL2
SDA2
R4
10k
R3
10k
3.3V
R5
10k
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