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參數(shù)資料
| 型號： | LTC4259A |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Quad IEEE 802.3af Power over Ethernet Controller with AC Disconnect |
| 中文描述： | 四IEEE 802.3af標(biāo)準(zhǔn)與AC電源斷開以太網(wǎng)控制器 |
| 文件頁數(shù)： | 25/32頁 |
| 文件大?。?/td> | 326K |
| 代理商： | LTC4259A |
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LTC4259A
25
4259Af
LTC4259A) by transmitting a START condition. A START
condition is generated by transitioning SDA from high to
low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition.
A STOP condition is generated by transitioning SDA from
low to high while SCL is high. The bus is then free for
communication with another SMBus or I
2
C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The corresponding SCL
clock pulse is always generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave must pull down the SDA line during
the Acknowledge clock pulse so that it remains a stable
LOW during the HIGH period of this clock pulse. When the
master is reading from a slave device, it is the master’s
responsibility to acknowledge receipt of the data byte in
the bit that follows unless the transaction is complete. In
that case the master will decline to acknowledge and issue
the STOP condition to terminate the communication.
Write Byte Protocol
The master initiates communication to the LTC4259A with
a START condition and a 7-bit bus address followed by the
Write Bit (Wr) = 0. If the LTC4259A recognizes its own
address, it acknowledges and the master delivers the com-
mand byte, signifying to which internal LTC4259A register
the master wishes to write. The LTC4259A acknowl
edges
and latches the lower five bits of the command byte into its
Register Address register. Only the lower five bits of the
command byte are checked by the LTC4259A; the upper
three bits are ignored. The master then delivers the data
byte. The LTC4259A acknowledges once more and latches
the data into the appropriate control register. Finally, the
master terminates the communication with a STOP condi-
tion. Upon reception of the STOP condition, the Register
Address register is cleared (see Figure7).
Read Byte Protocol
The master initiates communication from the LTC4259A
with a START condition and the same 7-bit bus address
followed by the Write Bit (Wr) = 0. If the LTC4259A
recognizes its own address, it acknowledges and the
master delivers the command byte, signifying which
internal LTC4259A register it wishes to read from. The
LTC4259A acknowledges and latches the lower five bits
of the command byte into its Register Address register. At
this time the master sends a REPEATED START condition
and the same 7-bit bus address followed by the Read Bit
(Rd) = 1. The LTC4259A acknowledges and sends the
contents of the requested register. Finally, the master
declines to acknowledge and terminates communication
with a STOP condition. Upon reception of the STOP
condition, the Register Address register is cleared (see
Figure 8).
Receive Byte Protocol
Since the LTC4259A clears the Register Address register
on each STOP condition, the interrupt register (register 0)
may be read with the Receive Byte Protocol as well as with
the Read Byte Protocol. In this protocol, the master
initiates communication with the LTC4259A with a START
condition and a 7-bit bus address followed by the Read Bit
(Rd) = 1. The LTC4259A acknowledges and sends the
contents of the interrupt register. The master then de-
clines to acknowledge and terminates communication
with a STOP condition (see Figure 9).
Alert Response Address and the INT Pin
In a system where several LTC4259As share a common INT
line, the master can use the Alert Response Address (ARA)
to determine which LTC4259A initiated the interrupt.
The master initiates the ARA procedure with a START
condition and the 7-bit ARA bus address (0001100)b
followed by the Read Bit (Rd) = 1. If an LTC4259A is
asserting the INT pin, it acknowledges and sends its 7-bit
bus address (010A
3
A
2
A
1
A
0
)b and a 1 (see Figure 10).
APPLICATIOU
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相關(guān)代理商/技術(shù)參數(shù) |
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| LTC4259A-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Synchronous No-Opto Flyback Controller |
| LTC4259ACGW | 功能描述:IC CTRLR POE QUAD AC DISC 36SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
| LTC4259ACGW#PBF | 功能描述:IC CTRLR POE QUAD AC DISC 36SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
| LTC4259ACGW#TR | 功能描述:IC CTRLR POE QUAD AC DISC 36SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
| LTC4259ACGW#TRPBF | 功能描述:IC CTRLR POE QUAD AC DISC 36SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
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