參數(shù)資料
型號(hào)： LTC3780
廠商： Linear Technology Corporation
英文描述： DIODE SCHOTTKY DUAL ISOLATED 25V 150mW 0.33V-vf 200mA-IFM 2mA-IF 0.5uA-IR SOT-563 3K/REEL
中文描述： 高效率，同步，四開(kāi)關(guān)降壓升壓控制器
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 421K
代理商： LTC3780
9
LTC3780
3780f
PIU
V
OSENSE
(Pin 6/Pin 4):
Error Amplifier Feedback Input. This
pin connects the error amplifier input to an external resis-
tor divider from V
OUT
.
SGND (Pin 7/Pin 5):
Signal Ground. All small-signal com-
ponents and compensation components should connect to
this ground, which should be connected to PGND at a single
point.
RUN (Pin 8/Pin 6):
Run Control Input. Forcing the RUN pin
below 1.5V causes the IC to shut down the switching regu-
lator circuitry. There is a 100k resistor between the RUN pin
and SGND in the IC. Do not apply >6V to this pin.
FCB (Pin 9/Pin 7):
Forced Continuous Control Input. The
voltage applied to this pin sets the operating mode of the
controller. When the applied voltage is less than 0.8V, the
forced continuous current mode is active. When this pin
is allowed to float, the burst mode is active in boost
operation and the skip cycle mode is active in buck
operation. When the pin is tied to INTV
CC
, the constant
frequency discontinuous current mode is active in buck or
boost operation.
PLLFLTR (Pin 10/Pin 8):
The Phase-Locked Loop’s Low-
pass Filter is Tied to This Pin. Alternatively, this pin can be
driven with an AC or DC voltage source to vary the frequency
of the internal oscillator.
PLLIN (Pin 11/Pin 10):
External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with 50k
. The phase-locked loop will force the rising
bottom gate signal of the controller to be synchronized with
the rising edge of the PLLIN signal.
STBYMD (Pin 12/Pin 11):
LDO Control Pin. Determines
whether the internal LDO remains active when the control-
ler is shut down. See Operation section for details. If the
STBYMD pin is pulled to ground, the SS pin is internally
pulled to ground, preventing start-up and thereby provid-
ing a single control pin for turning off the controller.
Decouple this pin with 0.1
μ
F if not tied to a DC potential.
(SSOP/QFN)
BOOST2, BOOST1 (Pins 13, 24/Pins 14, 27):
Boosted
Floating Driver Supply. The (+) terminal of the bootstrap ca-
pacitor C
A
and C
B
(Figure 11) connects here. The BOOST2
pin swings from a diode voltage below INTV
CC
up to V
IN
+
INTV
CC.
The BOOST1 pin swings from a diode voltage below
INTV
CC
up to V
OUT
+ INTV
CC
.
TG2, TG1 (Pins 14, 23/Pins 15, 26):
Top Gate Drive. Drives
the top N-channel MOSFET with a voltage swing equal to
INTV
CC
superimposed on the switch node voltage SW.
SW2, SW1 (Pins 15, 22/Pins 17, 24):
Switch Node. The
(–) terminal of the bootstrap capacitor C
A
and C
B
(Figure 11)
connects here. The SW2 pin swings from a Schottky diode
(external) voltage drop below ground up to V
IN
. The SW1
pin swings from a Schottky diode (external) voltage drop
below ground up to V
OUT
.
BG2, BG1 (Pins 16, 18/Pins 18, 20):
Bottom Gate Drive.
Drives the gate of the bottom N-channel MOSFET between
ground and INTV
CC
.
PGND (Pin 17/Pin 19):
Power Ground. Connect this pin
closely to the source of the bottom N-channel MOSFET, the
(–) terminal of CV
CC
and the (–) terminal of C
IN
(Figure 11).
INTV
CC
(Pin 19/Pin 21):
Internal 6V Regulator Output. The
driver and control circuits are powered from this voltage.
Decouple this pin to ground with a minimum of 4.7
μ
F low
ESR tantalum or ceramic capacitor.
EXTV
CC
(Pin 20/Pin 22):
External V
CC
Input. When EXTV
CC
exceeds 5.7V, an internal switch connects this pin to INTV
CC
and shuts down the internal regulator so that the controller
and gate drive power is drawn from EXTV
CC
. Do not exceed
7V at this pin and ensure that EXTV
CC
< V
IN
.
V
IN
(Pin 21/Pin 23):
Main Input Supply. Decouple this pin
to SGND with an RC filter (1
, 0.1
μ
F).
Exposed Pad (Pin 33, QFN Only):
This pin is SGND and
must be soldered to PCB ground.
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