參數(shù)資料
型號: LTC3780
廠商: Linear Technology Corporation
英文描述: DIODE SCHOTTKY DUAL ISOLATED 25V 150mW 0.33V-vf 200mA-IFM 2mA-IF 0.5uA-IR SOT-563 3K/REEL
中文描述: 高效率,同步,四開關(guān)降壓升壓控制器
文件頁數(shù): 24/28頁
文件大?。?/td> 421K
代理商: LTC3780
24
LTC3780
3780f
A low ESR (10m
) capacitor is selected. Input voltage
ripple is 65mV.
C
OUT
is chosen to filter the square current in Boost mode.
In this mode, the maximum output current peak is:
I
A
OUTPEAK MAXBUCK
,
(
,
)
5
%
.
=
(
)
=
12
5
1 13
13 6
A low ESR (5m
) capacitor is suggested. This capacitor
will limit output voltage ripple to 68mV.
PC Board Layout Checklist
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
Place C
IN
, Switch A, Switch B and D2 in one compact
area. Place C
OUT
, Switch C, Switch D and D1 in one
compact area.
Use immediate vias to connect the components (in-
cluding the LTC3780’s SGND and PGND pins) to the
ground plane. Use several large vias for each power
component.
Use planes for V
IN
and V
OUT
to maintain good voltage
filtering and to keep power losses low.
Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. Connect the copper areas to any
DC net (V
IN
or GND).
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3780. These items are also illustrated in Figure 11.
Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
sources of Switch B and Switch C.
Place Switch B and Switch C as close to the controller
as possible, keeping the PGND, BG and SW traces
short.
Keep the high dV/dT SW1, SW2, BOOST1, BOOST2, TG1
and TG2 nodes away from sensitive small-signal nodes.
The path formed by Switch A, Switch B, D2 and the C
IN
capacitor should have short leads and PC trace lengths.
The path formed by Switch C, Switch D, D1 and the C
OUT
capacitor also should have short leads and PC trace
lengths.
The output capacitor (–) terminals should be connected
as close as possible the (–) terminals of the input
capacitor.
Connect the INTV
CC
decoupling capacitor C
VCC
closely
to the INTV
CC
and PGND pins.
Connect the top driver boost capacitor C
A
closely to the
BOOST1 and SW1 pins. Connect the top driver boost
capacitor C
B
closely to the BOOST2 and SW2 pins.
Connect the input capacitors C
IN
and output capacitors
C
OUT
close to the power MOSFETs. These capacitors
carry the MOSFET AC current in Boost and Buck mode.
Connect V
OSENSE
pin resistive dividers to the (+) termi-
nals of C
OUT
and signal ground. A small V
OSENSE
decoupling capacitor should be as close as possible to
the LTC3780 SGND pin. The R2 connection should not
be along the high current or noise paths, such as the
input capacitors.
Route SENSE
and SENSE
+
leads together with mini-
mum PC trace spacing. The filter capacitor between
SENSE
+
and SENSE
should be as close as possible to
the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
Connect the I
TH
pin compensation network close to the
IC, between I
TH
and the signal ground pins. The capaci-
tor helps to filter the effects of PCB noise and output
voltage ripple voltage from the compensation loop.
APPLICATIU
W
U
U
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