參數(shù)資料
型號(hào)： LTC3773EUHF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 700 kHz SWITCHING FREQ-MAX, PQCC38
封裝： 5 X 7 MM, PLASTIC, MO-220WHKD, QFN-38
文件頁(yè)數(shù)： 19/32頁(yè)
文件大?。?/td> 461K
代理商： LTC3773EUHF
LTC3773
26
3773fa
that the minimum on-time of 130ns is not violated. The
minimum on-time occurs at maximum VIN:
t
V
Vf
V
VkHz
n
ON MIN
OUT
IN MAX
()
.
()
==
=
18
22 220
372 ss
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specication with a con-
servative maximum sense current threshold of 55mV:
R
mV
A
m
SENSE ≤≈
55
17 3
32
.
Use a commonly available 0.003
Ω sense resistor.
Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output voltage
but also to absorb the SENSE pin’s specied input current.
Rk
V
VV
k
V
MAX
OUT
130
06
24
30
06
24
()
.
=
=
118
30
.V
k
=
Choosing 1% resistors; R1 = 10k and R2 = 20k yields an
output voltage of 1.8V.
The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Renesas HAT2168H MOSFET
results in: RDS(ON) = 13.5mΩ, CMILLER = 6nC/25V = 240pF.
At maximum input voltage with T (estimated) = 50°C:
P
V
CC
MAIN=+
° °
[]
18
22
15
1
0 005 50
25
2
.
()
( .
)(
)
((.
)
(
)
(
)(
)
13 5
22
15
2
240
2
mV
A
pF
+
1
51 8
1
18
220
0 612
+
=
..
()
.
kHz
W
Using a Renesas HAT2165H as a bottom MOSFET, the
worst-case power dissipation by the synchronous MOSFET
under normal operating conditions at elevated ambient
temperature and an estimated 50°C junction temperature
rise is:
P
VV
V
mW
SYNC
=
=
22
1 8
22
15
1 125 5 3
1 23
2
.
(
) ( .
)( .
)
.
A short-circuit to ground will result in a folded back
current of
I
mV
ns
V
H
SC =
=
15
0 003
1
2
130
22
15
405
.
()
.
A
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 10. Check the following in the
PC layout:
1. Are the top N-channel MOSFETs located within 1cm of
each other with a common drain connection at CIN? Do
not attempt to split the input decoupling for the three
channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? Keep
the SGND at one end of a printed circuit path thus
preventing MOSFET currents from traveling under
the IC. The SGND pin should be used to hook up all
control circuitry on one side of the IC. The combined
LTC3773 SGND pin and the ground return of CVCC must
return to the combined COUT (–) terminals. The output
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the charge pump circuitry. The path formed by
the top N-channel MOSFET, Schottky diode and the CIN
capacitor should have short leads and PC trace lengths.
The power ground returns to the sources of the bottom
N-channel MOSFETs, anodes of the Schottky diodes
and (–) plates of CIN, which should have as short lead
lengths as possible.
3. The VCC decoupling capacitor should be placed immedi-
ately adjacent to the IC between the VCC pin and SGND.
A 1F ceramic capacitor of the X7R type is small enough
to t very close to the IC to minimize the ill effects of the
large current pulses drawn to drive the bottom MOSFETs.
An additional 4.7F to 10F of ceramic, tantalum or other
very low ESR capacitance is recommended in order to
keep the internal IC supply quiet.
4. Do the LTC3773 VFB resistive dividers connect to the (+)
terminals of COUT? The resistive divider must be con-
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