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參數(shù)資料
| 型號： | LTC3675EUFF#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC44 |
| 封裝： | 4 X 7 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-44 |
| 文件頁數(shù)： | 25/36頁 |
| 文件大?。?/td> | 413K |
| 代理商： | LTC3675EUFF#TRPBF |
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LTC3675
31
3675f
APPLICATIONS INFORMATION
Status Byte Read Back
When either the RSTB or IRQB pin is pulled low, it indicates
to the user that a fault condition has occurred. To nd out
the exact nature of the fault, the user can read the status reg-
isters. There are two status registers. One register provides
real time fault condition reporting while a second register
latches data when an interrupt has occurred. Figure 4
shows the operation of the real time and latched status
registers. The contents of the latched status register are
cleared when a CLRINT signal is issued. A PGOOD bit is
a ‘0’ if that regulator’s output voltage is more than 7.5%
below its programmed value.
The sub-address for the real time status register is 0Ch
and its format is as follows:
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
Unused
PGOOD6
PGOOD5
PGOOD4
PGOOD3
PGOOD2
PGOOD1
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
UV
OT
PGOOD6
PGOOD5
PGOOD4
PGOOD3
PGOOD2
PGOOD1
The sub-address for the latched status register is 0Dh and
its format is as follows:
A write operation cannot be performed to either of the
status registers.
PCB Considerations
When laying out the printed circuit board, the following
list should be followed to ensure proper operation of the
LTC3675:
1. The exposed pad of the package (pin 45) should connect
directly to a large ground plane to minimize thermal and
electrical impedance.
2. All the input supply pins must be tied together and each
supply pin should have a decoupling capacitor.
3. The switching regulator input supply pins and their re-
spective decoupling capacitors should be kept as short
as possible. The GND side of these capacitors should
connect directly to the ground plane of the part. These
capacitors provide the AC current to the internal power
MOSFETs and their drivers. It’s important to minimize
inductance from these capacitors to the VIN pins of the
LTC3675.
4. The switching power traces connecting SW1, SW2,
SW3, SW4, SW5, SWAB6, SWCD6 and SW7 to their
respective inductors should be minimized to reduce
radiated EMI and parasitic coupling. Due to the large
voltage swing of the switching nodes, high input im-
pedance sensitive nodes such as the feedback nodes
and LED_OV node should be kept far away or shielded
from the switching nodes or poor performance could
result.
5. The GND side of the switching regulator output capaci-
tors should connect directly to the thermal ground plane
of the part. Minimize the trace length from the output
capacitor to the inductor(s)/pin(s).
6. In a combined buck regulator application the trace length
of switch nodes to the inductor must be kept equal to
ensure proper operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC3676EUJ#PBF | 制造商:Linear Technology 功能描述: 制造商:Linear Technology 功能描述:DP-PMIC Multifunction, PMIC For Applications Processors |
| LTC3676EUJ-1#PBF | 制造商:Linear Technology 功能描述:IC CONV I.MX6 40QFN 制造商:Linear Technology 功能描述:DP-PMIC Multifunction, PMIC For Applications Processors |
| LTC3676IUJ#PBF | 制造商:Linear Technology 功能描述: 制造商:Linear Technology 功能描述:IC CONV I.MX6 40QFN 制造商:Linear Technology 功能描述:IC POWER MANAGEMENT SOLUTION 制造商:Linear Technology 功能描述:DP-PMIC Multifunction, PMIC For Applications Processors |
| LTC3676IUJ#TRPBF | 制造商:Linear Technology 功能描述:IC CONV I.MX6 40QFN |
| LTC3676IUJ-1#PBF | 制造商:Linear Technology 功能描述:IC CONV I.MX6 40QFN 制造商:Linear Technology 功能描述:IC POWER MANAGEMENT SOLUTION 制造商:Linear Technology 功能描述:IC, POWER MANAGEMENT SOLUTION, QFN-40 |
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