參數(shù)資料
型號(hào)： LTC3675EUFF#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC44
封裝： 4 X 7 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-44
文件頁(yè)數(shù)： 14/36頁(yè)
文件大?。?/td> 413K
代理商： LTC3675EUFF#TRPBF
LTC3675
21
3675f
OPERATION
POWER-UP AND POWER-DOWN VIA ENABLE PIN OR I2C
With the LTC3675 in its off state, a regulator can be enabled
either via its enable pin or I2C. In Figure 2c, buck regulator 1
is enabled via its enable pin at time t1. The WAKE pin goes
HIGH for 5 seconds and at t2 is pulled LOW. The buck
regulator stays enabled until time t3 when a hard reset
command is issued via I2C. The buck regulator powers
down and stays off for 1 second. At time t4, the LTC3675
exits from the power down state. Since the buck regula-
tor 1 is still enabled via its enable pin, it powers back up.
WAKE also gets pulled HIGH for 5 seconds. The RSTB
pin gets pulled HIGH 200ms after the buck regulator 1 is
in its PGOOD state.
LED CURRENT PROGRAMMING
The LED current is primarily controlled through the LED
DAC register at I2C sub-address 8. This register controls
an 8 bit current DAC. A 20k resistor placed between the
LED_FS pin and ground provides a current reference for the
DAC which results in 98μA of programmed LED current per
LSB. For example, programming a LED DAC register code
of 64h will result in a LED current of 9.8mA and a full-scale
setting of FFh will result in a LED current of 25mA.
The 2xFS bit which is bit 3 of the LED conguration reg-
ister at sub-address 7 effectively doubles the programmed
LED current. With a 20k resistor from LED_FS to ground
each LSB will be 196μA. Programming a LED DAC register
code of 64h will result in a LED current of 19.6mA and
a full-scale setting of FFh will result in an LED current of
50mA. The 2xFS mode is only intended for use when the
output voltage is below 20V.
I2C INTERFACE
The LTC3675 may communicate with a bus master using
the standard I2C 2-wire interface. The timing diagram
(Figure 2) shows the relationship of the signals on the
bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus accelerator,
are required on these lines. The LTC3675 is both a slave
receiver and slave transmitter. The I2C control signals,
SDA and SCL are scaled internally to the DVCC supply.
DVCC should be connected to the same power supply as
the bus pull-up resistors.
The I2C port has an undervoltage lockout on the DVCC pin.
When DVCC is below 1V, the I2C serial port is cleared and the
LTC3675 registers are set to their default congurations.
I2C Bus Speed
The I2C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I2C compliant master
device. It also contains input lters designed to suppress
glitches should the bus become corrupted.
Figure 3. I2C Bus Operation
tSU, DAT
tHD, STA
tHD, DAT
SDA
SCL
tSU, STA
tHD, STA
tSU, STO
3675 F03
tBUF
tLOW
tHIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
tr
tf
tSP
ACK
123
ADDRESS
WR
456789
123456789
00
0
1
0
1
0
010010
A7
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
ACK
STOP
START
SDA
SCL
DATA BYTE A
DATA BYTE B
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