參數(shù)資料
型號(hào)： LTC3541EDD#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 15/20頁(yè)
文件大小： 368K
描述： IC REG DL BCK/LINEAR SYNC 10-DFN
產(chǎn)品培訓(xùn)模塊： More Information on LDOs
標(biāo)準(zhǔn)包裝： 2,500
拓?fù)洌?/td> 降壓（降壓）同步（1），線性（LDO）（1）
功能： 任何功能
輸出數(shù)： 2
頻率 - 開(kāi)關(guān)： 2.25MHz
電壓/電流 - 輸出 1： 0.8 V ~ 5 V，500mA
電壓/電流 - 輸出 2： 0.4 V ~ 4.1 V，300mA
帶 LED 驅(qū)動(dòng)器： 無(wú)
帶監(jiān)控器： 無(wú)
帶序列發(fā)生器： 是
電源電壓： 0.9 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 帶卷 (TR)
LTC3541

3541fa
PPLICATIO S I FOR ATIO
U
U
proportional to frequency. Both the DC bias and gate charge
losses are proportional to V
IN
and thus their effects will
be more pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In con-
tinuous mode, the average output current flowing through
inductor L is chopped between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1  DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
3. Losses in the VLDO/linear regulator are due to the DC bias
currents as given in the Electrical Characteristics and to the
(V
IN
 V
OUT
) voltage drop across the internal output device
transistor.
Other losses when the buck and VLDO are in operation
(ENBUCK and ENVLDO equal logic high), including C
IN
and C
OUT
ESR dissipative losses and inductor core losses,
generally account for less than 2% total additional loss.
THERMAL CONSIDERATIONS
The LTC3541 requires the package backplane metal (GND
pin) to be well soldered to the PC board. This gives the
DFN package exceptional thermal properties. The power
handling capability of the device will be limited by the
maximum rated junction temperature of 125癈. The
LTC3541 has internal thermal limiting designed to protect
the device during momentary overload conditions. For
continuous normal conditions, the maximum junction
temperature rating of 125癈 must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat-spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through holes can also be used to spread the heat gener-
ated by power devices.
To avoid the LTC3541 exceeding the maximum junction
temperature, some thermal analysis is required. The goal
of the thermal analysis is to determine whether the power
dissipated exceeds the maximum junction temperature of
the part. The temperature rise is given by:
T
R
= P
D
" ?/DIV>
JA
where P
D
is the power dissipated by the regulator and ?/DIV>
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3541 with an input voltage
V
IN
of 2.9V, an LV
IN
voltage of 1.8V, an LV
OUT
voltage of
1.5V, a load current of 200mA for the buck, a load cur-
rent of 300mA for the VLDO and an ambient temperature
of 85癈. From the typical performance graph of switch
resistance, the R
DS(ON)
of the P-channel switch at 85癈 is
approximately 0.25?The R
DS(ON)
of the N-channel switch
is approximately 0.4? Therefore, power dissipated by the
part is approximately:
P
D
= (I
LOADBUCK
)
2
" R
SW
+ (I
LOADVLDO
)
"
(LV
IN
 LV
OUT
) = 167mW
For the 3mm ?3mm DFN package, the ?/DIV>
JA
is 43癈/W.
Thus, the junction temperature of the regulator is:
T
J
= 85癈 + (0.167)(43) = 92癈
which is well below the maximum junction temperature
of 125癈.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance R
DS(ON)
.
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