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參數(shù)資料
| 型號： | LTC2496CUHF#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 38-QFN |
| 標(biāo)準(zhǔn)包裝： | 52 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.9 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 38-QFN（5x7） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 16 個單端，雙極；8 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC1011A-B-ND - BOARD DELTA SIGMA ADC LTC2496 |
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LTC2496
2496fb
applicaTions inForMaTion
In order to achieve optimum performance, if an external
amplifier is not used, short these pins directly together
(ADCINP to MUXOUTP and ADCINN to MUXOUTN) and
minimize their capacitance to ground.
SERIAL INTERFACE PINS
The LTC2496 transmits the conversion result, reads the
input channel selection, and receives a start of conversion
command through a synchronous 3- or 4-wire interface.
Duringtheconversionandsleepstates,thisinterfacecanbe
usedtoaccesstheconverterstatus.Duringthedataoutput
state, it is used to read the conversion result and program
the input channel for the next conversion cycle.
Serial Clock Input/Output (SCK)
The serial clock pin (SCK) is used to synchronize the data
input/output transfer. Each bit is shifted out of the SDO
pin on the falling edge of SCK and data is shifted into the
SDI pin on the rising edge of SCK.
The serial clock pin (SCK) can be configured as either a
master (SCK is an output generated internally) or a slave
(SCK is an input and applied externally). Master mode
(Internal SCK) is selected by simply floating the SCK pin.
Slave mode (External SCK) is selected by driving SCK low
during power up and each falling edge of CS. Specific
details of these SCK modes are described in the Serial
Interface Timing Modes section.
Serial Data Output (SDO)
The serial data output pin (SDO) provides the result of the
last conversion as a serial bit stream (MSB first) during
the data output state. In addition, the SDO pin is used as
an end of conversion indicator during the conversion and
sleep states.
When CS is HIGH, the SDO driver is switched to a high
impedance state in order to share the data output line with
other devices. If CS is brought LOW during the conversion
phase, the EOC bit (SDO pin) will be driven HIGH. Once
the conversion is complete, if CS is brought LOW EOC will
be driven LOW indicating the conversion is complete and
the result is ready to be shifted out of the device.
Chip Select (CS)
The active low CS pin is used to test the conversion status,
enable I/O data transfer, initiate a new conversion, control
the duration of the sleep state, and set the SCK mode.
At the conclusion of a conversion cycle, while CS is HIGH,
the device remains in a low power sleep state where the
supply current is reduced several orders of magnitude. In
order to exit the sleep state and enter the data output state,
CS must be pulled low. Data is now shifted out the SDO pin
under control of the SCK pin as described previously.
A new conversion cycle is initiated either at the conclusion
of the data output cycle (all 24 data bits read) or by pulling
CS HIGH any time between the first and 24th rising edges
of the serial clock (SCK). In this case, the data output is
aborted and a new conversion begins.
Serial Data Input (SDI)
Theserialdatainput(SDI)isusedtoselecttheinputchannel.
Data is shifted into the device during the data output/input
state on the rising edge of SCK while CS is low.
OUTPUT DATA FORMAT
The LTC2496 serial output stream is 24 bits long. The
first bit indicates the conversion status, the second bit is
always zero, and the third bit conveys sign information.
The next 17 bits are the conversion result, MSB first. The
remaining 4 bits are always LOW.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available on the SDO pin during the
conversion and sleep states whenever CS is LOW. This
bit is HIGH during the conversion cycle, goes LOW once
the conversion is complete, and is HIGH-Z when CS is
HIGH.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit21(thirdoutputbit)istheconversionresultsignindica-
tor (SIG). If the selected input (VIN = IN+ – IN–) is greater
than 0V, this bit is HIGH. If VIN < 0, this bit is LOW.
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