參數(shù)資料
型號(hào)： LTC2496CUHF#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 3/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT DELTA SIG 38-QFN
標(biāo)準(zhǔn)包裝： 52
位數(shù)： 16
采樣率（每秒）： 6.9
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 800µW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 38-QFN（5x7）
包裝： 管件
輸入數(shù)目和類型： 16 個(gè)單端，雙極；8 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 1348 (CN2011-ZH PDF)
配用： DC1011A-B-ND - BOARD DELTA SIGMA ADC LTC2496
LTC2496
2496fb
applicaTions inForMaTion
CONVERTER OPERATION
Converter Operation Cycle
The LTC2496 is a multi-channel, low power, delta-sigma
analog-to-digital converter with an easy to use 4-wire
interface and automatic differential input current can-
cellation. Its operation is made up of three states (See
Figure 2). The converter operating cycle begins with the
conversion, followed by the sleep state and ends with the
data input/output cycle. The 4-wire interface consists of
serial data output (SDO), serial clock (SCK), chip select
(CS) and serial data input (SDI).The interface, timing,
operation cycle, and data output format is compatible with
Linear’s entire family of
ΔΣ converters.
Initially, at power up, the LTC2496 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, if CS is HIGH, power
consumption is reduced by two orders of magnitude. The
part remains in the sleep state as long as CS is HIGH. The
conversionresultisheldindefinitelyinastaticshiftregister
while the part is in the sleep state.
Once CS is pulled LOW, the device powers up, exits the
sleep mode, and enters the data input/output state. If CS
is brought HIGH before the first rising edge of SCK, the
device returns to the sleep state and the power is reduced.
If CS is brought HIGH after the first rising edge of SCK, the
data output cycle is aborted and a new conversion cycle
begins. The data output corresponds to the conversion
just completed. This result is shifted out on the serial
data output pin (SDO) under the control of the serial
clock pin (SCK). Data is updated on the falling edge of
SCK allowing the user to reliably latch data on the rising
edge of SCK (See Figure 3). The channel selection data for
the next conversion is also loaded into the device at this
time. Data is loaded from the serial data input pin (SDI)
on each rising edge of SCK. The data input/output cycle is
concluded once 24 bits are read out of the ADC or when
CS is brought HIGH. The device automatically initiates a
new conversion and the cycle repeats.
ThroughtimingcontroloftheCSandSCKpins,theLTC2496
offers several flexible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming and do not
disturbthecyclicoperationdescribedabove.Thesemodes
of operation are described in detail in the Serial Interface
Timing Modes section.
Ease of Use
The LTC2496 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multipleanaloginputsisstraightforward.Eachconversion,
immediately following a newly selected input, is valid and
accurate to the full specifications of the device.
The LTC2496 automatically performs offset and full scale
calibration every conversion cycle independent of the
input channel selected. This calibration is transparent to
the user and has no effect with the operation cycle de-
scribed above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage variation, input channel,
and temperature drift.
Easy Drive Input Current Cancellation
The LTC2496 combines a high precision delta-sigma ADC
with an automatic, differential, input current cancellation
Figure 2. LTC2496 State Transition Diagram
CONVERT
SLEEP
CHANNEL SELECT
DATA OUTPUT
POWER UP
IN+= CH0, IN–= CH1
2496 F02
CS = LOW
AND
SCK
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