rejection characteristics around DC and multiples of f
參數(shù)資料
型號(hào): LTC2495CUHF#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 24/34頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16BIT W/PGA 38-QFN
標(biāo)準(zhǔn)包裝: 52
位數(shù): 16
采樣率(每秒): 15
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 480µW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 38-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 38-QFN(5x7)
包裝: 管件
輸入數(shù)目和類型: 16 個(gè)單端,雙極;8 個(gè)差分,雙極
配用: DC1012A-C-ND - BOARD DELTA SIGMA ADC LTC2495
LTC2495
0
2495fd
Using the 2x speed mode of the LTC2495 alters the
rejection characteristics around DC and multiples of fS.
The device bypasses the offset calibration in order to
increase the output rate. The resulting rejection plots are
shown in Figures 27 and 28. 1x type frequency rejection
can be achieved using the 2x mode by performing a run-
ning average of the previous two conversion results (see
Figure 29).
Output Data Rate
When using its internal oscillator, the LTC2495 produces
upto15samplespersecond(sps)withanotchfrequencyof
60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignificantly short. When
operating with an external conversion clock (fO connected
to an external oscillator), the LTC2495 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
An increase in fEOSC over the nominal 307.2kHz will trans-
late into a proportional increase in the maximum output
data rate (up to a maximum of 100sps). The increase in
output rate leads to degradation in offset, full-scale error,
and effective resolution as well as a shift in frequency
rejection. When using the integrated temperature sensor,
the internal oscillator should be used or an external oscil-
lator fEOSC = 307.2kHz maximum.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejectionoflinefrequenciesremainsunchanged,thusfully
differential input signals with a high degree of symmetry
on both the IN+ and INpins will continue to reject line
frequency noise.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased above
1MHz(amorethan3xincreaseinoutputrate)theeffective-
ness of internal auto calibration circuits begins to degrade.
This results in larger offset errors, full-scale errors, and
decreased resolution, as seen in Figures 30 to 37.
Figure 27. Input Normal Mode Rejection 2x Speed Mode
Figure 28. Input Normal Mode Rejection 2x Speed Mode
applications inForMation
INPUT SIGNAL FREQUENCY (fN)
INPUT
NORMAL
REJECTION
(dB)
2495 F27
0
–20
–40
–60
–80
–100
–120
0
fN 2fN 3fN 4fN 5fN 6fN 7fN 8fN
INPUT SIGNAL FREQUENCY (fN)
INPUT
NORMAL
REJECTION
(dB)
2495 F28
0
–20
–40
–60
–80
–100
–120
250
248
252 254 256 258 260 262 264
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