參數(shù)資料
型號(hào): LTC2494CUHF
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
封裝: 5 X 7 MM, PLASTIC, MO-220WKHD, QFN-38
文件頁(yè)數(shù): 15/36頁(yè)
文件大?。?/td> 675K
代理商: LTC2494CUHF
LTC2494
2494fa
applicaTions inFormaTion
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 24th falling edge of SCk (see Figure 7). On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCk clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCk, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCk, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCk, the new channel
is still loaded, but the converter configuration remains
unchanged. In order to program both the input channel
and converter configuration, CS must go high after the
16th falling edge of SCk (at this point all data has been
shifted into the device).
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCk) signal (see Figure 8).
CS is permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is typically
concluded 4ms after VCC exceeds 2V. The level applied to
SCk at this time determines if SCk is internally generated
or externally applied. In order to enter the external SCk
mode, SCk must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
Figure 6. External Serial Clock, Single Cycle Operation
Hi-Z
2494 F06
Hi-Z
CS
SCK
(EXTERNAL)
SDI
SDO
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
VCC
FO
REF+
REF
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
10
F
0.1
F
LTC2494
2.7V TO 5.5V
4-WIRE
SPI INTERFACE
EOC
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
BIT 21
BIT 22
BIT 23
BIT 10 BIT 9
BIT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
GS2
GS1
GS0
ODD
DON'T CARE
MSB
SIG
“0”
相關(guān)PDF資料
PDF描述
LTC2494IUHF#TR 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
LTC2494IUHF 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
LTC2494CUHF#TR 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
LTC2495IUHF#TR 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
LTC2495CUHF#TR 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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LTC2495CUHF 制造商:Linear Technology 功能描述:ADC Single Delta-Sigma 15sps 16-bit Serial 38-Pin QFN EP