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參數(shù)資料
| 型號： | LTC2494CUHF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38 |
| 封裝： | 5 X 7 MM, PLASTIC, MO-220WKHD, QFN-38 |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 675K |
| 代理商： | LTC2494CUHF |
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LTC2494
2494fa
Figure 4. Internal PTAT Digital Output vs Temperature
Figure 5. Absolute Temperature Error
Table 6. LTC2494 Interface Timing Modes
CONFIGURATION
SCK
SOURCE
CONVERSION
CYCLE CONTROL
DATA OUTPUT
CONTROL
CONNECTION AND
WAVEFORMS
External SCk, Single Cycle
Conversion
External
CS and SCk
Figures 6, 7
External SCk, 3-Wire I/O
External
SCk
Figure 8
Internal SCk, Single Cycle
Conversion
Internal
CS
↓
CS
↓
Figures 9, 10
Internal SCk, 3-Wire I/O,
Continuous Conversion
Internal
Continuous
Internal
Figure 11
External Serial Clock, Single Cycle Operation
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 6).
Theexternalserialclockmodeisselectedduringthepower-
up sequence and on each falling edge of CS. In order to
enter and remain in the external SCk mode of operation,
SCk must be driven LOW both at power up and on each
CS falling edge. If SCk is HIGH on the falling edge of CS,
the device will switch to the internal SCk mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
When the device is in the sleep state, its conversion result
isheldinaninternalstaticshiftregister.Thedeviceremains
in the sleep state until the first rising edge of SCk is seen
while CS is LOW. The input data is then shifted in via the
SDIpinoneachrisingedgeofSCk(includingthefirstrising
edge). The channel selection and converter configuration
mode will be used for the following conversion cycle. If
the input channel or converter configuration is changed
during this I/O cycle, the new settings take effect on the
conversion cycle following the data input/output cycle.
The output data is shifted out the SDO pin on each falling
edge of SCk. This enables external circuitry to latch the
output on the rising edge of SCk. EOC can be latched on
the first rising edge of SCk and the last bit of the conver-
sion result can be latched on the 24th rising edge of SCk.
On the 24th falling edge of SCk, the device begins a new
conversion and SDO goes HIGH (EOC = 1) indicating a
conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
applicaTions inFormaTion
TEMPERATURE (K)
0
DATAOUT
16
480
640
800
960
1020
400
2494 F04
320
0
300
200
100
160
VCC = 5V
VREF = 5V
SLOPE = 2.45 LSB16/K
TEMPERATURE (
°C)
–55 –30
–5
ABSOLUTE
ERROR
(°
C)
5
4
3
2
1
–4
–3
–2
–1
0
120
95
70
45
20
2494 F05
–5
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