參數(shù)資料
型號(hào)： LTC2493IDE#TRPBF
廠(chǎng)商： Linear Technology
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT DELTA SIG 14-DFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 15
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 14-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 14-DFN-EP（4x3）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 4 個(gè)單端，雙極；2 個(gè)差分，雙極
配用： DC1010A-A-ND - BOARD DELTA SIGMA ADC LTC2493
LTC2493
20
2493fd
S
ACK
DATA
Sr
DATA TRANSFERRING
P
7-BIT ADDRESS
R/W
2493 F05
CONVERSION
SLEEP
DATA INPUT/OUTPUT
Figure 6. Conversion Sequence
Initiating a New Conversion
When the LTC2493 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device is
ready for a read operation. After the device acknowledges
a read request, the device exits the sleep state and enters
the data output state. The data output state concludes
and the LTC2493 starts a new conversion once a STOP
condition is issued by the master or all 32 bits of data are
read out of the device.
Duringthedatareadcycle,aSTOPcommandmaybeissued
by the master controller in order to start a new conversion
and abort the data transfer. This STOP command must be
issued during the ninth clock cycle of a byte read when
the bus is free (the ACK/NACK cycle).
LTC2493 Address
The LTC2493 has two address pins (CA0, CA1). Each may
be tied HIGH, LOW, or left floating enabling one of nine
possible addresses (see Table 5).
In addition to the configurable addresses listed in Table 5,
the LTC2493 also contains a global address (1110111)
whichmaybeusedforsynchronizingmultipleLTC2493sor
otherLTC24XXdelta-sigmaI2Cdevices(seeSynchronizing
Multiple LTC2493s with a Global Address Call section).
Operation Sequence
The LTC2493 acts as a transmitter or receiver, as shown
in Figure 6. The device may be programmed to perform
several functions. These include input channel selection,
measure the internal temperature, selecting the line fre-
quency rejection (50Hz, 60Hz, or simultaneous 50Hz and
60Hz) and a 2× speed mode.
Continuous Read
Inapplicationswheretheinputchannel/configurationdoes
not need to change for each cycle, the conversion can be
continuously performed and read without a write cycle
(see Figure 7). The configuration/input channel remains
unchanged from the last value written into the device. If
the device has not been written to since power-up, the
configuration is set to the default value. At the end of a
read operation, a new conversion automatically begins.
At the conclusion of the conversion cycle, the next result
may be read using the method described above. If the
conversion cycle is not concluded and a valid address
selects the device, the LTC2493 generates a NACK signal
indicating the conversion cycle is in progress.
applicaTions inForMaTion
Table 5. Address Assignment
CA1
CA0
ADDRESS
LOW
0010100
LOW
HIGH
0010110
LOW
Float
0010101
HIGH
LOW
0100110
HIGH
0110100
HIGH
Float
0100111
Float
LOW
0010111
Float
HIGH
0100101
Float
0100100
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