Frequency Rejection Selection (CA0/F0) The LTC2483 internal osci" />
參數(shù)資料
型號: LTC2483IDD#PBF
廠商: Linear Technology
文件頁數(shù): 7/34頁
文件大?。?/td> 0K
描述: IC ADC 16BIT I2C 10-DFN
標(biāo)準(zhǔn)包裝: 121
位數(shù): 16
采樣率(每秒): 6.8
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 480µW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 10-DFN(3x3)
包裝: 管件
輸入數(shù)目和類型: 1 個差分,雙極
產(chǎn)品目錄頁面: 1348 (CN2011-ZH PDF)
配用: DC955A-ND - BOARD DELTA SIGMA ADC LTC2483
LTC2483
2483fc
Frequency Rejection Selection (CA0/F0)
The LTC2483 internal oscillator provides better than 87dB
normal mode rejection at line frequencies of 50Hz and
60Hz and all of their harmonics (up to the 255th) from
48Hz to 62.4Hz.
When a fundamental rejection frequency different from
50Hz/60Hz is required or when the converter must be
synchronized with an outside source, the LTC2483 can
operate with an external conversion clock. The converter
applicaTions inFormaTion
automatically detects the presence of an external clock
signal at the CA0/F0 pin and turns off the internal oscilla-
tor. The chip address for CA0 is internally set HIGH. The
frequency fEOSC of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the HIGH and LOW periods tHEO and
tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2483 provides better than 110dB
SLEEP
DATA OUTPUT
START BY
MASTER
ACK BY
LTC2483
ACK BY
MASTER
NACK BY
MASTER
LSB
R
MSB
SGN
D15
7
8
9
1
2
9
1
2
3
4
5
6
7
8
9
1
7-BIT
ADDRESS
2483 F03
Figure 3. Timing Diagram for Reading from the LTC2483
S
ACK
DATA
Sr
DATA TRANSFERRING
P
SLEEP
DATA INPUT/OUTPUT
CONVERSION
7-BIT ADDRESS
R/W
2483 F04
Figure 4. The LTC2483 Conversion Sequence
7-BIT ADDRESS
CONVERSION
SLEEP
DATA OUTPUT
7-BIT ADDRESS
S
R
ACK
READ
P
2483 F05
Figure 5. Consecutive Reading at the Same Configuration
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