參數(shù)資料
型號(hào)： LTC2483IDD#PBF
廠商： Linear Technology
文件頁數(shù)： 16/34頁
文件大小： 0K
描述： IC ADC 16BIT I2C 10-DFN
標(biāo)準(zhǔn)包裝： 121
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，雙極
產(chǎn)品目錄頁面： 1348 (CN2011-ZH PDF)
配用： DC955A-ND - BOARD DELTA SIGMA ADC LTC2483
LTC2483
2483fc
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge trans-
ferred through the input and the reference pins. If large
external input and/or reference capacitors (CIN, CREF)
are used, the previous section provides formulae for
evaluating the effect of the source resistance upon the
converter performance for any value of fEOSC. If small
external input and/or reference capacitors (CIN, CREF) are
used, the effect of the external source resistance upon
the LTC2483 typical performance can be inferred from
Figures 9, 10, 11 and 12 in which the horizontal axis is
scaled by 307200/fEOSC.
applicaTions inFormaTion
Figure 20. Resolution (INLMAX ≤ 1 LSB) vs
Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION
(BITS)
12
16
18
22
10
50
70
2483 F20
14
20
40
90 100
20 30
60
80
TA = 85°C
TA = 25°C
VIN(CM) = VREF(CM)
VCC = VREF = 5V
CA0/F0 = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
Third, an increase in the frequency of the external oscil-
lator above 1MHz (a more than 3+ increase in the output
data rate) will start to decrease the effectiveness of the
internalautocalibrationcircuits.Thiswillresultinaprogres-
sive degradation in the converter accuracy and linearity.
Typicalmeasuredperformancecurvesforoutputdatarates
up to 100 readings per second are shown in Figures 16
to 23. In order to obtain the highest possible level of
accuracy from this converter at output data rates above
20 readings per second, the user is advised to maximize
the power supply voltage used and to limit the maximum
ambient operating temperature. In certain circumstances,
a reduction of the differential reference voltage may
be beneficial.
Figure 21. Offset Error vs Output
Data Rate and Reference Voltage
OUTPUT DATA RATE (READINGS/SEC)
0
–10
OFFSET
ERROR
(ppm
OF
V
REF
)
–5
5
10
20
10
50
70
2483 F21
0
15
40
90 100
20 30
60
80
VCC = 5V, VREF = 2.5V
VCC = VREF = 5V
VIN(CM) = VREF(CM)
VIN = 0V
CA0/F0 = EXT CLOCK
TA = 25°C
Figure 22. Resolution (NoiseRMS ≤ 1 LSB)
vs Output Data Rate and Reference Voltage
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION
(BITS)
12
16
18
20
24
10
50
70
2483 F22
14
22
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VIN = 0V
CA0/F0 = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/NOISERMS)
VCC = 5V, VREF = 2.5V
VCC = VREF = 5V
Figure 23. Resolution (INLMAX ≤ 1 LSB)
vs Output Data Rate and Reference Voltage
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION
(BITS)
12
16
18
22
10
50
70
2483 F23
14
20
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VIN = 0V
CA0/F0 = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
VCC = 5V, VREF = 2.5V
VCC = VREF = 5V
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